AMCC Proprietary 119
Revision 1.02 - September 10, 2007
PPC405 Processor
Preliminary User’s Manual
When an instruction-side machine check interrupt occurs, the PPC405 stores the address of the excepting
instruction in SRR2. When a data-side machine check occurs, the PPC405 stores the address of the next
sequential instruction in SRR2. Simultaneously, for all machine check interrupts, the contents of the MSR are
loaded into SRR3.
The MSR Machine Check Enable bit (MSR[ME]) is reset to 0 to disable another machine check from interrupting
the machine check interrupt handling routine. The other MSR bits are loaded with the values shown in Table 6-5
and Table 6-6 on page 120. The high-order 16 bits of the program counter are then written with the contents of the
EVPR and the low-order 16 bits of the program counter are written with 0x0200. Interrupt processing begins at the
new address in the program counter.
Executing an rfci instruction restores the program counter from SRR2 and the MSR from SRR3, and execution
resumes at the address in the program counter.
6.7.1 Instruction Machine Check Handling
When a machine check occurs on an instruction fetch, and execution of that instruction is subsequently attempted,
a machine check—instruction interrupt occurs. If enabled by MSR[ME], the processor reports the machine check—
instruction interrupt by vectoring to the machine check handler (EVPR[0:15] || 0x0200), setting. Note that only a
bus error can cause a machine check—instruction interrupt. Taking the vector automatically clears MSR[ME] and
the other MSR fields.
Note that it is improper to declare a machine check—instruction interrupt when the instruction is fetched, because
the address is possibly the result of an incorrect speculation by the fetcher. It is quite likely that no attempt will be
made to execute an instruction from the erroneous address. The interrupt will occur only if execution of the
instruction is subsequently attempted.
When a machine check occurs on an instruction fetch, the erroneous instruction is never validated in the instruction
cache unit (ICU). Fetch requests to cacheable memory that miss in the ICU cause an instruction cache line fill
(eight words). If any words in the fetched line are associated with an error, an interrupt occurs upon attempted
execution and the cache line is invalidated. If any word in the line is in error, the cache line is invalidated after the
line fill.
is set, even if MSR[ME] = 0. This means that if a machine check—instruction interrupt occurs while running in code
in which MSR[ME] is disabled, the machine check—instruction interrupt is recorded, but no interrupt occurs.
Software running with MSR[ME] disabled can sample to determine whether at least one machine check—
instruction interrupt occurred during the disabled execution.
If a new machine check—instruction interrupt occurs after MSR[ME] is enabled again, the new machine check—
instruction interrupt is recorded, and the machine check—instruction interrupt handler is invoked. However,
enabling MSR[ME] again does not cause a machine Check interrupt to occur simply due to the presence of
indicating that a machine check—instruction interrupt occurred while MSR[ME] was disabled. The machine
check—instruction interrupt must occur while MSR[ME] is enabled for the machine check interrupt to be taken.
Software should, in general, clear the bits before returning from a machine check interrupt to avoid any ambiguity
when handling subsequent machine check interrupts.
Table 6-5. Register Settings during Machine Check—Instruction Interrupts
SRR2 Written with the address that caused the machine check.
SRR3 Written with the contents of the MSR
PC EVPR[0:15] || 0x0200
ESR MCI ← 1. All other bits are cleared.
To Next Page
Loading...