96 AMCC Proprietary
Revision 1.02 - September 10, 2007
PPC405 Processor
Preliminary User’s Manual
G (guarded,1 bit)
When set (TLBLO_entry[G] = 1), indicates that the hardware cannot speculatively access the location for pre-
fetching or out-of-order load access. The G storage attribute is typically used to protect memory-mapped I/O from
inadvertent access. Attempted execution of an instruction from a guarded data storage address while instruction
address translation is enabled results in an instruction storage interrupt because data storage and memory
mapped I/O (MMIO) addresses are not used to contain instructions.
An instruction fetch from a guarded region does not occur until the execution pipeline is empty, thus guaranteeing
that the access is necessary and therefore not speculative. For this reason, performance is degraded when
executing out of guarded regions, and software should avoid unnecessarily marking regions of instruction storage
as guarded.
In real mode, the Storage Guarded Register (SGR) controls guarding.
U0 (user-defined attribute, 1 bit)
When set (TLBLO[U0] = 1), indicates the user-defined attribute applies to the data in the associated page.
In real mode, the Storage User-defined 0 Register (SU0R) controls the setting of the U0 storage attribute.
E (endian, 1 bit)
When set (TLBLO[E] = 1), indicates that data in the associated page is stored in true little endian format.
In real mode, the Storage Little-Endian Register (SLER) controls the setting of the E storage attribute.
5.3.3 Shadow Instruction TLB
To enhance performance, four instruction-side TLB entries are kept in a four-entry fully-associative shadow array.
This array, called the instruction TLB (ITLB), helps to avoid TLB contention between instruction accesses to the
TLB and load/store operations. Replacement and invalidation of the ITLB entries is managed by hardware. See
“Shadow TLB Consistency” on page 97 for details.
The ITLB can be considered a level-1 instruction-side TLB; the UTLB serves as the level-2 instruction-side TLB.
The ITLB is used only during instruction fetches for storing instruction address translations. Each ITLB entry
contains the translation information for a page. The processor uses the ITLB for address translation of instruction
accesses when MSR[IR] = 1.
5.3.3.1 ITLB Accesses
The instruction unit accesses the ITLB independently of the rest of the MMU. ITLB accesses are transparent to the
executing program, except that ITLB hits contribute to higher overall instruction throughput by allowing data
address translations to occur in parallel. Therefore, when instruction accesses hit in the ITLB, the address
translation mechanisms in the UTLB are available for use by data accesses simultaneously.
The ITLB requests a new entry from the UTLB when an ITLB miss occurs. A four-cycle latency occurs at each ITLB
miss that is also a UTLB hit; the latency is longer if it is also a UTLB miss, or if there is contention for the UTLB from
the data side. A round-robin replacement algorithm replaces existing entries with new entries.
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