AMCC Proprietary 115
Revision 1.02 - September 10, 2007
PPC405 Processor
Preliminary User’s Manual
6.5.2 Save/Restore Registers 0 and 1 (SRR0–SRR1)
SRR0 and SRR1 are 32-bit registers that hold the interrupted machine context when a noncritical interrupt is
processed. On interrupt, SRR0 is set to the current or next instruction address and the contents of the MSR are
written to SRR1. When an rfi instruction is executed at the end of the interrupt handler, the program counter and
the MSR are restored from SRR0 and SRR1, respectively.
The contents of SRR0 and SRR1 can be written into GPRs using the
mfspr instruction. The contents of GPRs can
be written to SRR0 and SRR1 using the
mtspr instruction.
6.5.3 Save/Restore Registers 2 and 3 (SRR2–SRR3)
SRR2 and SRR3 are 32-bit registers that hold the interrupted machine context when a critical interrupt is
processed. On interrupt, SRR2 is set to the current or next instruction address and the contents of the MSR are
written to SRR3. When an rfci instruction is executed at the end of the interrupt handler, the program counter and
the MSR are restored from SRR2 and SRR3, respectively.
The contents of SRR2 and SRR3 can be written to GPRs using the mfspr instruction. The contents of GPRs can
be written to SRR2 and SRR3 using the mtspr instruction.
27 DR Data Relocate
0 Data address translation is disabled.
1 Data address translation is enabled.
28:31
Reserved
Figure 6-2. Save/Restore Register 0 (SRR0)
0:29 SRR0 receives an instruction address when a non-
critical interrupt is taken; the Program Counter is
restored from SRR0 when the
rfi instruction
executes.
30:31
Reserved
Figure 6-3. Save/Restore Register 1 (SRR1)
0:31 SRR1 receives a copy of the MSR when an
interrupt is taken; the MSR is restored from SRR1
when
rfi executes.
Figure 6-4. Save/Restore Register 2 (SRR2)
0:29 SRR2 receives an instruction address when a
critical interrupt is taken; the Program Counter is
restored from SRR2 when
rfci executes.
30:31
Reserved
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