AMCC PPC405 - Figure 7-6. Timer Status Register (TSR); Timer Control Register (TCR); Timer Status Register (TSR)

AMCC Proprietary 135
Revision 1.01 - February 19, 2007
PPC405 Processor
Preliminary User’s Manual
7.4 Timer Status Register (TSR)
The TSR can be accessed for read or write-to-clear.
Status registers are generally set by hardware and read and cleared by software. The mfspr instruction reads the
TSR. Clearing the TSR is performed by writing a word to the TSR, using mtspr, having a 1 in all fields to be cleared
and a 0 in all other fields. The data written to the TSR is not direct data, but a mask. A 1 clears the field and a 0 has
no effect.
7.5 Timer Control Register (TCR)
The TCR controls PIT, FIT, and watchdog timer operation.
The TCR[WRC] field is cleared to 0 by all processor resets. This field is set only by software. However, hardware
does not allow software to clear the field after it is set. After software writes a 1 to a bit in the field, that bit remains
a 1 until any reset occurs. This prevents errant code from disabling the watchdog timer reset function.
All processor resets clear TCR[ARE] to 0, disabling the auto-reload feature of the PIT.
Figure 7-6. Timer Status Register (TSR)
0ENW
Enable Next Watchdog
0 Action on next watchdog event is to set
TSR[ENW] = 1.
1 Action on next watchdog event is governed by
TSR[WIS].
Software must reset TSR[ENW] = 0 after each
watchdog timer event.
1WIS
Watchdog Interrupt Status
0 No Watchdog interrupt is pending.
1 Watchdog interrupt is pending.
2:3 WRS
Watchdog Reset Status
00 No Watchdog reset has occurred.
01 Core reset was forced by the watchdog.
10 Chip reset was forced by the watchdog.
11 System reset was forced by the watchdog.
4PIS
PIT Interrupt Status
0 No PIT interrupt is pending.
1 PIT interrupt is pending.
5FIS
FIT Interrupt Status
0 No FIT interrupt is pending.
1 FIT interrupt is pending.
6:31
Reserved