AMCC Proprietary 71
Revision 1.02 - September 10, 2007
PPC405 Processor
Preliminary User’s Manual
3.3.1 ICU Operations
Instructions from cacheable memory regions are copied into the instruction cache array. The fetcher can access
instructions much more quickly from a cache array than from memory. Cache lines are loaded either target-word-
first or sequentially. Target-word-first fills start at the requested word, continue to the end of the line, and then wrap
to fill the remaining words at the beginning of the line. Sequential fills start at the first word of the cache line and
proceed sequentially to the last word of the line.
The bypass path handles instructions in cache-inhibited memory and improves performance during line fill
operations. If a request from the fetcher obtains an entire line from memory, the queue does not have to wait for
the entire line to reach the cache. The target word (the word requested by the fetcher) is sent on the bypass path to
the queue while the line fill proceeds, even if the selected line fill order is not target-word-first.
Cache line fills always run to completion, even if the instruction stream branches away from the rest of the line. As
requested instructions are received, they go to the fetcher from the fill register before the line fills in the cache. The
filled line is always placed in the ICU; if an external memory subsystem error occurs during the fill, the line is not
written to the cache. During a clock cycle, the ICU can send two instructions to the fetcher.
3.3.2 Instruction Cachability Control
When instruction address translation is enabled (MSR[IR] = 1), instruction cachability is controlled by the I storage
attribute in the translation lookaside buffer (TLB) entry for the memory page. If TLB_entry[I] = 1, caching is
inhibited; otherwise caching is enabled. Cachability is controlled separately for each page, which can range in size
from 1KB to 16MB. Translation Lookaside Buffer (TLB) on page 92 describes the TLB.
When instruction address translation is disabled (MSR[IR] = 0), instruction cachability is controlled by the
Instruction Cache Cachability Register (ICCR). Each field in the ICCR (ICCR[S0:S31]) controls the cachability of a
128MB region (see Real-Mode Storage Attribute Control on page 105). If ICCR[Sn] = 1, caching is enabled for the
specified region; otherwise, caching is inhibited.
The performance of the PPC405 is significantly lower while fetching instructions from cache inhibited regions.
Following system reset, address translation is disabled and all ICCR bits are reset to 0 so that no memory regions
are cacheable. Before regions can be designated as cacheable, the ICU cache array must be invalidated. The iccci
instruction must execute before the cache is enabled. Address translation can then be enabled, if required, and the
TLB or the ICCR can then be configured for the required cachability.
3.3.3 Instruction Cache Synonyms
The following information applies only if instruction address translation is enabled (MSR[IR] = 1) and 1KB or 4KB
page sizes are used. See Memory Management on page 91 for information about address translation and page
sizes.
An instruction cache synonym occurs when the instruction cache array contains multiple cache lines from the same
real address. Such synonyms result from combinations of:
• Cache array size
• Cache associativity
• Page size
• The use of effective addresses (EAs) to index the cache array
For example, the instruction cache array has a "way size" of 8KB (16KB array/2 ways). Thus, 11 bits (EA
19:29
) are
needed to select a word (instruction) in each way. For the minimum page size of 1KB, the low order eight bits
(EA
22:29
) address a word in a page. The high order address bits (EA
0:21
) are translated to form a real address
(RA), which the ICU uses to perform the cache tag match. Cache synonyms could occur because the index bits
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