126 AMCC Proprietary
Revision 1.02 - September 10, 2007
PPC405 Processor
Preliminary User’s Manual
To clear a FIT interrupt, the interrupt handling routine must clear the FIT interrupt bit, TSR[FIS]. Clearing is
performed by writing a word to TSR, using an mtspr instruction, that has 1 in any bit positions to be cleared and 0
in all other bit positions. The data written to the TSR is not direct data, but a mask; a 1 clears a bit and 0 has no
effect.
Executing an rfi instruction restores the program counter from SRR0 and the MSR from SRR1, and execution
resumes at the address in the program counter.
6.16 Watchdog Timer Interrupt
For a general description of the PPC405 timer facilities, see Timer Facilities on page 129 The watchdog timer
(WDT) is described in Watchdog Timer on page 133.
If the WDT interrupt is enabled by TCR[WIE] and MSR[CE], the PPC405 initiates a WDT interrupt after detecting
the first WDT time-out. First time-out is detected when, at the beginning of a clock cycle, TSR[WIS] = 1. (This
occurs on the second cycle after the 0→1 transition of the appropriate time-base bit while TSR[ENW] = 1 and
TSR[WIS] = 0.) The PPC405 immediately takes the interrupt. The address of the next sequential instruction is
saved in SRR2; simultaneously, the contents of the MSR are written into SRR3 and the MSR is written with the
values shown in Table 6-17. The high-order 16 bits of the program counter are then written with the contents of the
EVPR and the low-order 16 bits of the program counter are written with 0x1020. Interrupt processing begins at the
address in the program counter.
To clear the WDT interrupt, the interrupt handling routine must clear the WDT interrupt bit TSR[WIS]. Clearing is
done by writing a word to TSR (using
mtspr), with a 1 in any bit position that is to be cleared and 0 in all other bit
positions. The data written to the status register is not direct data, but a mask; a 1 causes the bit to be cleared, and
a 0 has no effect.
Executing the return from critical interrupt instruction (rfci) restores the contents of the program counter and the
MSR from SRR2 and SRR3, respectively, and the PPC405 resumes execution at the contents of the program
counter.
Table 6-16. Register Settings during Fixed Interval Timer Interrupts
SRR0 Written with the address of the next sequential instruction
SRR1 Written with the contents of the MSR
PC EVPR[0:15] || 0x1010
TSR FIS ← 1
Table 6-17. Register Settings during Watchdog Timer Interrupts
SRR2 Written with the address of the next sequential instruction
SRR3 Written with the contents of the MSR
PC EVPR[0:15] || 0x1020
TSR WIS ← 1
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