AMCC Proprietary 95
Revision 1.02 - September 10, 2007
PPC405 Processor
Preliminary User’s Manual
5.3.2.3 Access Control Fields
Several access controls are available in the UTLB entries.
ZSEL (zone select, 4 bits)
Selects one of 16 zone fields (Z0—Z15) from the Zone Protection Register (ZPR). The ZPR field bits can modify
the access protection specified by the TLB_entry[V, EX, WR] bits of a TLB entry. Zone protection is described in
detail in “Zone Protection” on page 103.
EX (execute enable, 1 bit)
When set (TLBLO_entry[EX] = 1), enables instruction execution at addresses within a page. ZPR settings can
override TLBLO_entry[EX]; see “Zone Protection” on page 103, for more information.
WR (write-enable 1 bit)
When set (TLBLO_entry[WR] = 1), enables store operations to addresses in a page. ZPR settings can override
TLBLO_entry[WR]; see “Zone Protection” on page 103.
5.3.2.4 Storage Attribute Fields
TLB entries contain bits that control and provide information about the storage control attributes. Four of the
attributes (W, I, M, and G) are defined in the PowerPC Architecture. The E storage attribute is defined in the
PowerPC Embedded Environment.
W (write-through,1 bit)
When set (TLBLO_entry[W] = 1), stores are specified as write-through. If data in the referenced page is in the data
cache, a store updates the cached copy of the data and the external memory location. Contrast this with a write-
back strategy, which updates memory only when a cache line is flushed.
In real mode, the Data Cache Write-through Register (DCWR) controls the write strategy.
Note that the PowerPC Architecture does not support memory models in which write-through is enabled and
caching is inhibited. It is considered a programming error to use these memory models; the results are undefined.
I (caching inhibited,1 bit)
When set (TLBLO_entry[I] = 1), a memory access is completed by using the location in main memory, bypassing
the cache arrays. During the access, the accessed location is not put into the cache arrays.
In real mode, the Instruction Cache Cachability Register (ICCR) and Data Cache Cachability Register (DCCR)
control cachability. In these registers, the setting of the bit is reversed; 1 indicates that a storage control region is
cacheable, rather than caching inhibited.
Note that the PowerPC Architecture does not support memory models in which write-through is enabled and
caching is inhibited. It is considered a programming error to use these memory models; the results are undefined.
It is considered a programming error if the target location of a load/store, dcbz, or fetch access to caching inhibited
storage is in the cache; the results are undefined. It is not considered a programming error for the target locations
of other cache control instructions to be in the cache when caching is inhibited.
M (memory coherent,1 bit)
For implementations that support multiprocessing, the M storage attribute improves the performance of memory
coherency management. Because the PPC405 does not provide multi-processor support or hardware support for
data coherency, the M bit is implemented, but has no effect.
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