AMCC Proprietary 60
Revision 1.02 - September 10, 2007
PPC405 Processor
Preliminary User’s Manual
isync guarantees that all subsequent instructions are fetched and executed using the context established by all
previous instructions. isync is a context synchronizing operation; isync causes all subsequently prefetched
instructions to be discarded and refetched.
The following example illustrates the use of isync with debug exceptions:
mtdbcr0 Enable an instruction address compare (IAC) event
isync Wait for the new Debug Control Register 0 (DBCR0) context to be established
XYZ This instruction is at the IAC address; an isync was necessary to guarantee that the
IAC event occurs at the execution of this instruction
2.10.2 Execution Synchronization
Execution synchronization is a subset of context synchronization. An execution synchronizing operation satisfies
the first two requirements of context synchronizing operations, but not the latter two. That is, execution
synchronizing operations guarantee that preceding instructions execute in the “old” context, but do not guarantee
that subsequent instructions operate in the “new” context.
There are three execution synchronizing operations: eieio, mtmsr, and sync. Note that all context synchronizing
instructions are also implicitly execution synchronizing, since context synchronization is a superset of execution
synchronization.
Because mtmsr is execution synchronizing, it guarantees that previous instructions complete using the old MSR
value. (For example, using mtmsr to change the endian mode.) However, to guarantee that subsequent
instructions use the new MSR value, we have to insert a context synchronization operation, such as isync.
Note that PowerPC Book-E imposes additional requirements on updates to MSR[EE] (the external interrupt enable
bit). Specifically, if a mtmsr, wrtee, or wrteei instruction sets MSR[EE] = 1, and an External Input, Decrementer, or
Fixed Interval Timer exception is pending, the interrupt must be taken before the instruction that follows the
MSR[EE]-updating is executed. In this sense, these MSR[EE]-updating instructions can be thought of as being
context synchronizing with respect to the MSR[EE] bit, in that it guarantees that subsequent instructions execute
(or are prevented from executing and an interrupt taken) according to the new context of MSR[EE].
Finally, while sync and eieio are execution synchronizing, they are also more restrictive in their requirement of
memory ordering. Stating that an operation is execution synchronizing does not imply storage ordering. This is an
additional specific requirement of sync and eieio.
2.10.3 Storage Ordering and Synchronization
Storage synchronization enforces ordering between storage access instructions executed by the
PPC405. The
sync instruction guarantees that all previous storage references complete with respect to the
PPC405 before the
sync instruction completes (therefore, before any subsequent instructions begin to execute). The sync instruction
is execution synchronizing. Consider the following use of sync:
Consider the following use of
sync:
stw Store to peripheral
sync Wait for store to actually complete
mtdcr Reconfigure device
The eieio instruction guarantees the order of storage accesses. All storage accesses that precede eieio complete
before any storage accesses that follow the instruction, as in the following example:
stb X Store to peripheral, address X; this resets a status bit in the device
eieio Guarantee stb X completes before next instruction
lbz Y Load from peripheral, address Y; this is the status register updated by
stb X.
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