AMCC PPC405 - 2.3.1 General Purpose Registers; 2.3.2 Special Purpose Registers

AMCC Proprietary 35
Revision 1.02 - September 10, 2007
PPC405 Processor
Preliminary User’s Manual
2.3.1 General Purpose Registers (GPR0-GPR31)
The PPC405 contains thirty-two 32-bit general purpose registers (GPRs). Data from memory can be read into
GPRs using load instructions and the contents of GPRs can be written to memory using store instructions. Most
integer instructions use GPRs for source and destination operands. See Table 10-1 on page 353 for the numbering
of the GPRs.
2.3.2 Special Purpose Registers (SPR)
Special purpose registers (SPRs), which are part of the PowerPC Architecture and the PowerPC Embedded
Environment, are accessed using the mtspr and mfspr instructions.
SPRs control the operation of debug facilities, timers, interrupts, storage control attributes, and other architected
processor resources. Table 10-3 on page 354 shows the mnemonic, name, and number for each SPR. Table 2-1
on page 36, lists the PPC405 SPRs by function and indicates the pages where the SPRs are described more fully.
Except for the Link Register (LR), the Count Register (CTR), the Fixed-point Exception Register (XER), User SPR
General 0 (USPRG0, and read access to SPR General 4–7 (SPRG4–SPRG7), all SPRs are privileged. As SPRs,
the registers TBL and TBU are privileged write-only; as TBRs, these registers can be read in user mode. Unless
used to access non-privileged SPRs, attempts to execute mfspr and mtspr instructions while in user mode cause
privileged violation program interrupts. See Privileged SPRs on page 57.
Figure 2-3. General Purpose Registers (GPR0-GPR31)
0:31 General Purpose Register data