AMCC Proprietary 111
Revision 1.02 - September 10, 2007
PPC405 Processor
Preliminary User’s Manual
Except for machine checks, all PPC405 interrupts are handled precisely:
• The address of the excepting instruction (for synchronous exceptions, other than the system call exception) or
the address of the next sequential instruction (for asynchronous exceptions and the system call exception) is
passed to the interrupt handling routine.
• All instructions that precede the instruction whose address is reported to the interrupt handling routine have
completed execution and that no subsequent instruction has begun execution. The specific instruction whose
address is reported might not have begun execution or might have partially completed, as specified for each
interrupt type.
6.3 Interrupt Handling Priorities
The PPC405 processor handles only one interrupt at a time. Multiple simultaneous interrupts are handled in the
priority order shown in Table 6-1 (assuming, of course, that the interrupt types are enabled). Multiple interrupts can
exist simultaneously, each of which requires the generation of an interrupt. The architecture does not provide for
simultaneously reporting more than one interrupt of the same class (critical or non-critical). Therefore, interrupts
are ordered with respect to each other. A masking mechanism is available for certain persistent interrupt types.
When an interrupt type is masked, and an event causes an exception which would normally generate an interrupt
of that type, the exception persists as a status bit in a register. However, no interrupt is generated. Later, if the
interrupt type is enabled (unmasked), and the exception status has not been cleared by software, the interrupt due
to the original exception event is finally generated.
All asynchronous interrupt types can be masked. In addition, certain synchronous interrupt types can be masked.
Table 6-1. Interrupt Handling Priorities
Priority Interrupt Type
Critical or
Noncritical
Causative Conditions
1 Machine check—data Critical External bus error during data-side access
2 Debug—IAC Critical IAC debug event (in internal debug mode)
3 Machine check—instruction Critical Attempted execution of instruction for which an external bus error occurred
during fetch
4 Debug—EXC, UDE Critical EXC or UDE debug event (in internal debug mode)
5 Critical interrupt input Critical Active level on the critical interrupt input by the UIC
6 Watchdog timer—first time-out Critical Posting of an enabled first time-out of the watchdog timer in the TSR
7 Instruction TLB Miss Noncritical Attempted execution of an instruction at an address and process ID for which
a valid matching entry was not found in the TLB
8 Instruction storage —
ZPR[Z
n]=00
Noncritical Instruction translation is active, execution access to the translated address is
not permitted because ZPR[Zn] = 00 in user mode, and an attempt is made to
execute the instruction
9 Instruction storage —
TLB_entry[EX] = 0
Noncritical Instruction translation is active, execution access to the translated address is
not permitted because TLB_entry[EX] = 0, and an attempt is made to execute
the instruction
Instruction storage —
TLB_entry[G] = 1 or
SGR[G
n]=1
Noncritical Instruction translation is active, the page is marked guarded, and an attempt is
made to execute the instruction
10 Program Noncritical Attempted execution of illegal instructions, TRAP instruction, privileged
instruction in problem state
System call Noncritical Execution of the sc instruction
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