AMCC Proprietary 139
Revision 1.02 - September 10, 2007
PPC405 Processor
Preliminary User’s Manual
8.3.4 JTAG Implementation
PPC405 JTAG interface I/Os (TDI, TDO, TMs, TCK, and
TRST) are 5V tolerant and do not contain internal pull up
resistors.
The optional JTAG instructions, idcode and highz, offer additional JTAG functionality. The idcode instruction returns
the PPC405 JTAG ID, which is unique for each chip version. The highz instruction disables all chip outputs
regardless of whether they are included in the JTAG boundary scan chain.
The PPC405 provides boundary scan structures on all digital I/O signals.
PPC405 boundary scan structures are defined as follows:
1. All digital pins labeled in the IOSpeclist as functional inputs are observe only.
2. All digital pins labeled as outputs are drive only and are always actively driven during JTAG except when the
HIGHZ command is selected on the JTAG TAP controller.
3. All digital pins labeled as 3-state ouputs or bidirectional drive when explicitly enabled by means of the
appropriate boundary scan cell. They are forced to a disabled state in the presence of the HIGHZ command.
When the driver is disabled, the input state of a bidirectional signal can be observed.
4. Analog pins are not observable.
8.3.5 JTAG ID Register
In most cases, there is a register that enables manufacturing, part number, and version information to be
determined through the TAP. The
mfdcr instruction is used to read this register.
Refer to data sheet for the chip in question to see the value assigned to the JTAG ID.
8.4 Trace Port
The PPC405 implements a trace status interface to support the tracing of code running in real-time. This interface
enables the connection of an external trace tool, such as RISCWatch, and allows for user-extended trace
functions. A software tool with trace capability, such as RISCWatch with RISCTrace, can use the data collected
from this port to trace code running on the processor. The result is a trace of the code executed, including code
executed out of the instruction cache if it was enabled. Information on trace capabilities, how trace works, and how
to connect the external trace tool is available in
RISCWatch Debugger User’s Guide.
8.5 Debug Modes
The PPC405 supports the following debug modes, each of which supports a type of debug tool or debug task
commonly used in embedded systems development:
• Internal debug mode, which supports ROM monitors
• External debug mode, which supports JTAG debuggers
• Debug wait mode, which supports processor stopping or stepping for JTAG debuggers while servicing
interrupts
• Real-time trace mode, which supports trigger events for real-time tracing
Internal and external debug modes can be enabled simultaneously. Both modes are controlled by fields in Debug
Control Register 0 (DBCR0). Real-time trace mode is available only if internal, external, and debug wait modes are
disabled.
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