AMCC PPC405 - 5. Memory Management; 5.1 MMU Overview; 5.2 Address Translation

AMCC Proprietary 91
Revision 1.02 - September 10, 2007
PPC405 Processor
Preliminary User’s Manual
5. Memory Management
The PPC405 memory management unit (MMU) performs address translation and protection functions. With
appropriate system software, the MMU supports:
• Translation of effective addresses to real addresses
• Independent enabling of instruction and data address translation and protection
• Page-level access control using the translation mechanism
• Software control of page replacement strategy
• Additional virtual-mode control of protection using zones
• Real-mode write protection
5.1 MMU Overview
The instruction and integer units generate 32-bit effective addresses (EAs) for instruction fetches and data
accesses, respectively. Instruction EAs are generated for sequential instruction fetches, and for instruction fetches
causing changes in program flow (branches and interrupts). Data EAs are generated for load/store and cache
control instructions. The MMU translates EAs into real addresses; the instruction cache unit (ICU) and data cache
unit (DCU) use real addresses to access memory.
The PPC405 MMU supports demand-paged virtual memory and other memory management schemes that depend
on precise control of effective to real address mapping and flexible memory protection. Translation misses and
protection faults cause precise interrupts. Sufficient information is available to correct the fault and restart the
faulting instruction.
The MMU divides storage into pages. A page represents the granularity of EA translation and protection controls.
Eight page sizes (1KB, 4KB, 16KB, 64KB, 256KB, 1MB, 4MB, 16MB) are simultaneously supported. A valid entry
for a page containing the EA to be translated must be in the translation lookaside buffer (TLB) for address
translation to be performed. EAs for which no valid TLB entry exists cause TLB-miss interrupts.
5.2 Address Translation
Fields in the Machine State Register (MSR) control the use of the MMU for address translation. The instruction
relocate (IR) field of the MSR controls translation for instruction accesses. The data relocate (DR) field of the MSR
controls the translation mechanism for data accesses. These fields, specified independently, can be changed at
any time by a program in supervisor state. Note that all interrupts clear MSR[IR, DR] and place the processor in the
supervisor state. Subsequent discussion about translation and protection assumes that MSR[IR, DR] are set,
enabling address translation.
The processor references memory when it fetches an instruction, and when it executes load/store, branch, and
cache control instructions. Processor accesses to memory use EAs to references a memory location. When
translation is enabled, the EA is translated into a real address, as illustrated in Figure 5-1 on page 92. The ICU or
DCU uses the real address for the access. (When translation is not enabled, the EA is already a real address.)
In address translation, the EA is combined with an 8-bit process ID (PID) to create a 40-bit virtual address. The
virtual address is compared to all of the TLB entries. A matching entry supplies the real address for the storage
reference. Figure 5-1 on page 92 illustrates the process.