140 AMCC Proprietary
Revision 1.02 - September 10, 2007
PPC405 Processor
Preliminary User’s Manual
8.5.1 Internal Debug Mode
Internal debug mode provides access to architected processor resources and supports setting hardware and
software breakpoints and monitoring processor status. In this mode, debug events generate debug interrupts,
which can interrupt normal program flow so that monitor software can collect processor status and alter processor
resources.
Internal debug mode relies on exception handling software at a dedicated interrupt vector and an external
communications path to debug software problems. This mode, used while the processor executes instructions,
enables debugging of operating system or application programs.
In this mode, debugger software is accessed through a communications port, such as a serial port, external to the
processor core.
To enable internal debug mode, the Debug Control Register 0 (DBCR0) field IDM is set to 1 (DBCR0[IDM] = 1). To
enable debug interrupts, MSR[DE] = 1. A debug interrupt occurs on a debug event only if DBCR0[IDM] = 1 and
MSR[DE] = 1.
8.5.2 External Debug Mode
External debug mode provides access to architected processor resources and supports stopping, starting, and
stepping the processor, setting hardware and software breakpoints, and monitoring processor status. In this mode,
debug events cause the processor to become architecturally frozen. While the processor is frozen, normal
instruction execution stops and architected processor resources can be accessed and altered. External bus activity
continues in external debug mode.
The JTAG mechanism can pass instructions to the processor for execution, allowing a JTAG debugger to display
and alter processor resources, including memory.
The JTAG mechanism prevents the occurrence of a privileged exception when a privileged instruction is executed
while the processor is in user mode.
Storage access control by a memory management unit (MMU) remains in effect while in external debug mode; the
debugger may need to modify MSR or TLB values to access protected memory.
Because external debug mode relies only on internal processor resources, it can be used to debug system
hardware and software.
In this mode, access to the processor is through the JTAG debug port.
To enable external debug mode, DBCR0[EDM] = 1. To enable debug interrupts, MSR[DE] = 1. A debug interrupt
occurs on a debug event only if DBCR0[EDM] = 1 and MSR[DE] = 1.
8.5.3 Debug Wait Mode
In debug wait mode, debug events cause the PPC405 to enter a state in which interrupts can be serviced while the
processor appears to be stopped.
Debug wait mode provides access to architected processor resources in a manner similar to external debug mode,
except that debug wait mode allows the servicing of interrupt handlers. It supports stopping, starting, and stepping
the processor, setting hardware and software breakpoints, and monitoring processor status. In this mode, if a
debug event caused the processor to become architecturally frozen, an interrupt causes the processor to run an
interrupt handler and return to the architecturally frozen state upon returning from the interrupt handler. While the
processor is frozen, normal instruction execution stops and architected processor resources can be accessed and
altered. External bus activity continues in debug wait mode.
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