AMCC Proprietary 21
Revision 1.02 - September 10, 2007
PPC405 Processor
Preliminary User’s Manual
1. Overview
This document describes the PowerPC™ 405 fixed-point, 32-bit RISC processor, referred to as the PPC405.
This section describes:
• PPC405 processor features
• PPC405 as a 32-bit implementation of Book-E Enhanced PowerPC Architecture.
• Organization of the PPC405 core, including a block diagram and descriptions of the functional units.
• PPC405 core interfaces.
1.1 PPC405 Processor Features
The PPC405 provides high performance and low-power consumption executing at sustained speeds approaching
one cycle per instruction. On-chip instruction and data caches reduce chip count and design complexity in systems
and improve system throughput. The CPU provides an ideal foundation for systems incorporating system-on-a-
chip (SOC) designs. This section provides a list of features that are implemented in the PPC405.
• Five-stage pipeline with single-cycle execution of most instructions, including loads and stores
• Unaligned load/store support to cache arrays, main memory, and on-chip memory (OCM)
• Thirty-two 32-bit general purpose registers (GPRs)
• Static branch prediction
• Hardware multiply/divide for faster integer arithmetic (4-cycle multiply, 35-cycle divide)
• Multiply-accumulate instructions
• Enhanced string and multiple-word handling
• True little endian operation
• Forward and reverse trace from a trigger event
• Storage control
• Separate, configurable, two-way set-associative 16KB instruction and data cache units
• Eight words (32 bytes) per cache line
• Instruction cache unit (ICU) non-blocking during line fills, data cache unit (DCU) non-blocking during line
fills and flushes
• Read and write line buffers
• Instruction fetch hits are supplied from line buffer
• Data load/store hits are supplied to line buffer
• Programmable ICU prefetching of next sequential line into line buffer
• Programmable ICU prefetching of non cacheable instructions, full line (eight words) or half line (four words)
• Write-back or write-through DCU write strategies
• Programmable allocation on loads and stores
• Operand forwarding during cache line fills
• Parity detection and reporting for the instruction cache, data cache, and translation lookaside buffer (TLB)
• Double word instruction fetch from cache
• Translation of the 4 GB logical address space into physical addresses
• On-Chip Memory (OCM) interface
• Memory management
• Translation of the 4GB logical address space into physical addresses
• Independent enabling of instruction and data translation/protection
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