AMCC Proprietary 53
Revision 1.02 - September 10, 2007
PPC405 Processor
Preliminary User’s Manual
BO[4] is the prediction reversal bit. If BO[4] = 0, the default prediction is applied. If BO[4] = 1, the reverse of the
standard prediction is applied. For the cases in Table 2-14 where BO[4] =
y, software can reverse the default
prediction. This should only be done when the default prediction is likely to be wrong. Note that for the “branch
always” condition, reversal of the default prediction is not allowed.
The PowerPC Architecture requires assemblers to provide a way to conveniently control branch prediction. For any
conditional branch mnemonic, a suffix may be added to the mnemonic to control prediction, as follows:
+ Predict branch to be taken
− Predict branch to be not taken
For example,
bcctr+ causes BO[4] to be set appropriately to force the branch to be predicted taken.
2.8 Speculative Accesses
The PowerPC Architecture permits implementations to perform speculative accesses to memory, either for
instruction fetching, or for data loads. A speculative access is defined as any access which is not required by a
sequential execution model.
For example, prefetching instructions beyond an undetermined conditional branch is a speculative fetch; if the
branch is not in the predicted direction, the program, as executed, never needs the instructions from the predicted
path.
Sometimes speculative accesses are inappropriate. For example, attempting to fetch instructions from addresses
that cannot contain instructions can cause problems.To protect against errant accesses to “sensitive” memory or
I/O devices, the PowerPC Architecture provides the G (guarded) storage attribute, which can be used to specify
memory pages from which speculative accesses are prohibited. (Actually, speculative accesses to guarded
storage are allowed in certain limited circumstances; if an instruction in a cache block will be executed, the rest of
the cache block can be speculatively accessed.)
2.8.1 Speculative Accesses in the PPC405
The PPC405 does not perform speculative loads.
Two methods control speculative instruction fetching. If instruction address translation is enabled (MSR[IR] = 1),
the G (guarded) field in the translation lookaside buffer (TLB) entries controls speculative accesses.
If instruction address translation is disabled (MSR[IR] = 0), the Storage Guarded Register (SGR) controls
speculative accesses for regions of memory. When a region is guarded (speculative fetching is disallowed),
instruction prefetching is disabled for that region. A fetch request must be completely resolved (no longer
speculative) before it is issued. There is a considerable performance penalty for fetching from guarded storage, so
guarding should be used only when required.
Note that, following any reset, the PPC405 operates with all of storage guarded.
Note that when address translation is enabled, attempts to fetch from guarded storage result in instruction storage
exceptions. Guarded memory is in most often needed with peripheral status registers that are cleared
automatically after being read, because an unintended access resulting from a speculative fetch would cause the
loss of status information. Because the MMU provides 64 pages with a wide range of page sizes as small as 1KB,
fetching instructions from guarded storage should be unnecessary.
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