AMCC Proprietary 3
Revision 1.02 - September 10, 2007
PPC405 Processor
Preliminary User’s Manual
Contents
Figures.................................................................................................................................................. 11
Tables ................................................................................................................................................... 13
About This Book.................................................................................................................................. 17
1. Overview .......................................................................................................................................... 21
1.1 PPC405 Processor Features .................................................................................................................... 21
1.2 PowerPC Architecture .............................................................................................................................. 22
1.3 PPC405 as a PowerPC Implementation ................................................................................................... 23
1.4 RISC Processor Core Organization .......................................................................................................... 23
1.4.1 Instruction and Data Cache Controllers .......................................................................................... 23
1.4.1.1 Instruction Cache Unit ............................................................................................................. 23
1.4.1.2 Data Cache Unit ...................................................................................................................... 23
1.4.2 Memory Management Unit .............................................................................................................. 24
1.4.3 Debug .............................................................................................................................................. 25
1.4.3.1 Development Tool Support ...................................................................................................... 25
1.4.3.2 Debug Modes .......................................................................................................................... 25
1.4.4 Processor Core Interfaces .............................................................................................................. 26
1.4.4.1 Processor Local Bus ................................................................................................................ 26
1.4.4.2 Device Control Register Bus .................................................................................................... 26
1.4.4.3 Clock and Power Management ................................................................................................ 26
1.4.4.4 JTAG ........................................................................................................................................ 26
1.4.4.5 Interrupts .................................................................................................................................. 26
1.4.4.6 On-Chip Memory ..................................................................................................................... 26
1.5 Processor Programming Model ................................................................................................................ 26
1.5.1 Data Types ...................................................................................................................................... 26
1.5.2 Processor Register Set Summary ................................................................................................... 27
1.5.2.1 General Purpose Registers ..................................................................................................... 27
1.5.2.2 Special Purpose Registers ...................................................................................................... 27
1.5.2.3 Machine State Register ........................................................................................................... 27
1.5.2.4 Condition Register ................................................................................................................... 27
1.5.2.5 Device Control Registers ......................................................................................................... 27
1.5.3 Memory-Mapped I/O Registers ....................................................................................................... 28
1.5.4 Addressing Modes .......................................................................................................................... 28
2. Programming Model ....................................................................................................................... 31
2.1 User and Privileged Programming Models ............................................................................................... 31
2.2 Storage Addressing .................................................................................................................................. 31
2.2.1 Storage Attributes ........................................................................................................................... 32
2.3 Registers .................................................................................................................................................. 32
2.3.1 General Purpose Registers (GPR0-GPR31) ................................................................................... 35
2.3.2 Special Purpose Registers (SPR) ................................................................................................... 35
2.3.2.1 Count Register (CTR) .............................................................................................................. 36
2.3.2.2 Link Register (LR) .................................................................................................................... 37
2.3.2.3 Fixed Point Exception Register (XER) ..................................................................................... 37
2.3.2.4 Special Purpose Registers (USPRG0 and SPRG0–SPRG7) ................................................. 39
2.3.2.5 Processor Version Register (PVR) .......................................................................................... 39
2.3.3 Condition Register (CR) .................................................................................................................. 39
2.3.3.1 CR Fields After Compare Instructions ..................................................................................... 40
2.3.3.2 The CR0 Field .......................................................................................................................... 40
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