AMCC PPC405 - Appendix C. Code Optimization and Instruction Timings; C.1 Code Optimization Guidelines; C.1.1 Condition Register Bits for Boolean Variables; C.1.2 CR Logical Instruction for Compound Branches

AMCC Proprietary 430
Revision 1.02 - September 10, 2007
PPC405 Processor
Preliminary User’s Manual
Appendix C.
Code Optimization and Instruction Timings
The code optimization guidelines in “Code Optimization Guidelines” and the information describing instruction
timings in Instruction Timings on page 431 can help compiler, system, and application programmers produce high-
performance code and determine accurate execution times.
C.1 Code Optimization Guidelines
The following guidelines can help to reduce program execution times.
C.1.1 Condition Register Bits for Boolean Variables
Compilers can use Condition Register (CR) bits to store boolean variables, where 0 and 1 represent False and
True values, respectively. This generally improves performance, compared to using General Purpose Registers
(GPRs) to store boolean variables. Most common operations on boolean variables can be accomplished using the
CR Logical instructions.
C.1.2 CR Logical Instruction for Compound Branches
For example, consider the following pseudocode:
if (Var28 || Var29 || Var30 || Var 31) branch to target
Var28–Var31 are boolean variables, maintained as bits in the CR[CR7] field (CR
28:31
). The value 1 represents
True; 0 represents False.
This could be coded with branches as:
bt 28, target
bt 29, target
bt 30, target
bt 31, target
Generally faster, functionally equivalent code, using CR Logical instructions, follows:
crcr 2, 28, 29
cror 2, 2, 30
cror 2, 2, 31
bt 2, target
C.1.3 Cache Usage
Code and data can be organized, based on the size and structure of the instruction and data cache arrays, to
minimize cache misses.
In the cache arrays, any two addresses in which A
m:26
(the index) are the same, but which differ in A
0:m-1
(the tag),
are called congruent. (This describes a two-way set-associative cache.) A
27:31
define the 32 bytes in a cache line,
the smallest object that can be brought into the cache. Only two congruent lines can be in the cache
simultaneously; accessing a third congruent line causes the removal from the cache of one of the two lines
previously there
Table C-1 illustrates the value of
m and the index size for the various cache array sizes.