AMCC PPC405 - 2. Programming Model; 2.1 User and Privileged Programming Models; 2.2 Storage Addressing

AMCC Proprietary 31
Revision 1.02 - September 10, 2007
PPC405 Processor
Preliminary User’s Manual
2. Programming Model
The programming model of the PPC405 describes how the following features and operations of the processor
appear to programmers:
• Memory organization and addressing, page 31
• Registers, page 32
• Data types and alignment, page 42
• Byte ordering, page 44
• Instruction processing, page 49
• Branch processing, page 50
• Speculative accesses, page 53
• Privileged mode operation, page 56.
• Synchronization, page 58
• Instruction set, page 61
2.1 User and Privileged Programming Models
The PPC405 executes programs in two modes, also referred to as states. Programs running in privileged mode
(also referred to as the supervisor state) can access any register and execute any instruction. These instructions
and registers comprise the privileged programming model. In user mode, certain registers and instructions are
unavailable to programs. This is also called the problem state. Those registers and instructions that are available
comprise the user programming model.
Privileged mode provides operating system software access to all processor resources. Because access to certain
processor resources is denied in user mode, application software runs in user mode. Operating system software
and other application software is protected from the effects of an errant application program.
Throughout this book, the terms user program and privileged programs are used to associate programs with one of
the programming models. Registers and instructions are described as user or privileged. Privileged mode
operation is described in detail in User and Supervisor Modes on page 56.
2.2 Storage Addressing
As a 32-bit implementation of the Book-E Enhanced PowerPC Architecture, the PPC405 implements a uniform 32-
bit effective address (EA) space. Effective addresses are expanded into virtual addresses and then translated to
36-bit (64GB) real addresses by the memory management unit (see Memory Management on page 91 for more
information on the translation process).
The PPC405 generates an effective address whenever it executes a storage access, branch, cache management,
or translation look aside buffer (TLB) management instruction, or when it fetches the next sequential instruction.