AMCC PPC405 - Debug Control Register 1 (DBCR1); Figure 8-2. Debug Control Register 1 (DBCR1)

144 AMCC Proprietary
Revision 1.02 - September 10, 2007
PPC405 Processor
Preliminary User’s Manual
8.8.1.2 Debug Control Register 1 (DBCR1)
15 IA34X
Instruction Address Exclusive Range Compare 3–4:
0Inclusive
1 Exclusive
Selects range defined by IAC3 and IAC4 to be
inclusive or exclusive.
16 IA12T
Instruction Address Range Compare 1-2 Toggle:
0Disabled
1 Enable
Toggles range 12 inclusive, exclusive
DBCR[IA12X] on debug event.
17 IA34T
Instruction Address Range Compare 3–4 Toggle:
0Disabled
1 Enable
Toggles range 34 inclusive, exclusive
DBCR[IA34X] on debug event.
18:30
Reserved
31 FT
Freeze Timers on Debug Event:
0 Timers not frozen
1 Timers frozen
Figure 8-2. Debug Control Register 1 (DBCR1)
0D1R
DAC1 Read Debug Event:
0 Disabled
1 Enabled
1D2R
DAC 2 Read Debug Event:
0 Disabled
1 Enabled
2D1W
DAC 1 Write Debug Event:
0 Disabled
1 Enabled
3D2W
DAC 2 Write Debug Event:
0 Disabled
1 Enabled
4:5 D1S
DAC 1 Size:
00 Compare all bits
01 Ignore lsb (least significant bit)
10 Ignore two lsbs
11 Ignore five lsbs
Address bits used in the compare:
Byte address
Halfword address
Word address
Cache line (8-word) address
6:7 D2S
DAC 2 Size:
00 Compare all bits
01 Ignore lsb (least significant bit)
10 Ignore two lsbs
11 Ignore five lsbs
Address bits used in the compare:
Byte address
Halfword address
Word address
Cache line (8-word) address
8DA12
Enable Data Address Range Compare 1:2:
0 Disabled
1 Enabled
Registers DAC1 and DAC2 define an address
range used for DAC address comparisons
9 DA12X
Data Address Exclusive Range Compare 1:2:
0 Inclusive
1 Exclusive
Selects range defined by DAC1 and DAC2
to be inclusive or exclusive
10:11
Reserved