AMCC PPC405 - DCU Instructions

76 AMCC Proprietary
Revision 1.02 - September 10, 2007
PPC405 Processor
Preliminary User’s Manual
3.5.2 DCU Instructions
Data cache flushes and fills are triggered by load, store and cache control instructions. Cache control instructions
are provided to fill, flush, or invalidate cache blocks.
The following instructions control data cache operations:
icbi
Instruction Cache Block Invalidate
Invalidates a cache block.
icbt
Instruction Cache Block Touch
Initiates a block fill, enabling a program to begin a cache block fetch before the program
needs an instruction in the block.
The program can subsequently branch to the instruction address and fetch the
instruction without incurring a cache miss.
This is a privileged instruction.
iccci
Instruction Cache Congruence Class Invalidate
Invalidates the instruction cache array.
This is a privileged instruction.
icread
Instruction Cache Read
Reads either an instruction cache tag entry or an instruction word from an instruction
cache line, typically for debugging. Fields in CCR0 control instruction behavior (see
Cache Control and Debugging Features on page 77).
This is a privileged instruction.
dcba
Data Cache Block Allocate
Speculatively establishes a line in the cache and marks the line as modified.
If the line is not currently in the cache, the line is established and marked as modified
without actually filling the line from external memory.
If dcba references a non cacheable address,
dcba is treated as a no-op.
If dcba references a cacheable address, write-through required (which would otherwise
cause an alignment exception),
dcba is treated as a no-op.
dcbf
Data Cache Block Flush
Flushes a line, if found in the cache and marked as modified, to external memory; the
line is then marked invalid.
If the line is found in the cache and is not marked modified, the line is marked invalid but
is not flushed.
This operation is performed regardless of whether the address is marked cacheable.
dcbi
Data Cache Block Invalidate
Invalidates a block, if found in the cache, regardless of whether the address is marked
cacheable. Any modified data is not flushed to memory.
This is a privileged instruction.
dcbst
Data Cache Block Store
Stores a block, if found in the cache and marked as modified, into external memory; the
block is not invalidated but is no longer marked as modified.
If the block is marked as not modified in the cache, no operation is performed.
This operation is performed regardless of whether the address is marked cacheable.