AMCC PPC405 - External Interrupt; External Interrupt Handling; Table 6-8. Register Settings During Instruction Storage Interrupts; Table 6-9. Register Settings During External Interrupts

122 AMCC Proprietary
Revision 1.02 - September 10, 2007
PPC405 Processor
Preliminary User’s Manual
6.10 External Interrupt
External interrupts (external to the processor core) are triggered by active levels non-critical interrupts in the UIC.
All external interrupting events are presented to the processor as a single external interrupt. External interrupts are
enabled or disabled by MSR[EE].
Programming Note: MSR[EE] also enables PIT and FIT interrupts. However, after timer interrupts, control
passes to different interrupt vectors than for the interrupts discussed in the preceding paragraph. Therefore,
these timer interrupts are described in Programmable Interval Timer (PIT) Interrupt on page 125 and Fixed
Interval Timer (FIT) Interrupt on page 125.
6.10.1 External Interrupt Handling
When MSR[EE] = 1 (external interrupts are enabled), a noncritical external interrupt occurs, and this interrupt is the
highest priority interrupt condition, the processor immediately writes the address of the next sequential instruction
into SRR0. Simultaneously, the contents of the MSR are saved in SRR1.
When the processor takes a noncritical external interrupt, MSR[EE] is set to 0. This disables other external
interrupts from interrupting the interrupt handler before SRR0 and SRR1 are saved. The MSR is also written with
the other values shown in Table 6-9. The high-order 16 bits of the program counter are written with the contents of
the EVPR and the low-order 16 bits of the program counter are written with 0x0500. Interrupt processing begins at
the address in the program counter.
Executing an rfi instruction restores the program counter from SRR0 and the MSR from SRR1, and execution
resumes at the address in the program counter.
Table 6-8. Register Settings during Instruction Storage Interrupts
SRR0 Set to the EA of the instruction for which execute access was not permitted
SRR1 Set to the value of the MSR at the time of the interrupt
PC EVPR[0:15] || 0x0400
ESR DIZ ← 1If access failure due to a zone protection fault (ZPR[Z
n] = 00 in user
mode)
Note: If ESR[DIZ] is not set, the interrupt occurred because TBL_entry[EX]
was clear in an otherwise accessible zone, or because of an instruction fetch
from a storage region marked as guarded. See “Exception Syndrome Register
(ESR)” on page 116 for details of ESR operation.
MCI ← unchanged
All other bits are cleared.
Table 6-9. Register Settings during External Interrupts
SRR0 Written with the address of the next sequential instruction
SRR1 Written with the contents of the MSR
PC EVPR[0:15] || 0x0500