AMCC PPC405 - C.2.8 Loads and Store Misses; C.2.9 Instruction Cache Misses

AMCC Proprietary 435
Revision 1.02 - September 10, 2007
PPC405 Processor
Preliminary User’s Manual
C.2.8 Loads and Store Misses
Cacheable stores that miss in the DCU, and non cacheable stores, are queued internally in the DCU so that the
store instruction appears to execute in one cycle. Under certain conditions, the DCU can pipeline up to three store
instructions. (See the Cache Operations on page 69 for more information.)
Because the PPC405 can execute instructions that follow load misses if no load-use dependency exists, the load
and the “using” instruction should be separated by “non-using” instructions whenever possible. The number of load
miss penalty cycles incurred by a load that misses in the DCU or DCU line fill buffer is reduced by one cycle for
every non-use instruction following the load. When the number of non-use instructions following the load is equal to
or greater than the number of cycles that it takes to obtain the load data, the load instruction appears to execute in
a single cycle. The number of cycles that it takes to obtain load data when it misses in the data cache and line fill
buffer depends on whether operand forwarding is enabled or disabled and the system memory timing.
C.2.9 Instruction Cache Misses
Refer to Instruction Processing on page 49 for detailed information about the instruction queue and instruction
fetching. Table C-2 illustrates instruction cache penalties for cacheable and non cacheable fetches that miss in the
ICU array and line fill buffer.
Table C-2 assumes that:
• The PPC405 and processor local bus (PLB) run at the same frequency
• The PLB returns an address acknowledge during the first cycle in which the DCU asserts the PLB request
• The target instruction is returned in the cycle following the address acknowledge cycle
The penalty cycles shown for sequential ICU requests assume that the DCD stage and pre-fetch queue are filled
with single-cycle non branching instructions or BKNT branch instructions. The penalty cycles for the remaining two
rows are for taken branches from DCD and PFB0, respectively.
Table C-2. Instruction Cache Miss Penalties
Type of ICU Request Miss Penalty Cycles
Sequential
3
Branch Taken from DCD
5
Branch Taken from PFB0
4