AMCC Proprietary 56
Revision 1.02 - September 10, 2007
PPC405 Processor
Preliminary User’s Manual
The use of these regions could be reversed (code in Region 1 and I/O devices in Region 2), if Region 2 is set as
guarded. Prefetching from the highest addresses of Region 1 could cause an attempt to speculatively access the
bottom of Region 2, but guarding prevents this from occurring. The performance penalty is slight, under the
assumption that code infrequently executes the instructions in the highest addresses of Region 1.
2.8.3 Summary
Software should take the following actions to prevent speculative accesses to sensitive data areas, if the sensitive
data areas are not in guarded storage:
• Protect against accesses to “random” values in the LR or CTR on
blr or bctr branches following rfi, rfci, or sc
instructions by putting appropriate instructions before or after the
rfi, rfci, or sc instruction. See Fetching Past
an Interrupt-Causing or Interrupt-Returning Instruction on page 54.
• Protect against “running past” the end of memory into a bordering I/O device by putting an unconditional
branch at the end of the memory area. See Fetching Past an Unconditional Branch on page 55.
• Recognize that a maximum of 19 words can be prefetched past an unresolved conditional branch, either down
the target path or the sequential path. See Prefetch Distance Down an Unresolved Branch Path on page 54.
Of course, software should not code branches with known unsafe targets (either relative to the instruction counter,
or to addresses contained in the LR or CTR), on the assumption that the targets are “protected” by code
guaranteeing that the unsafe direction is not taken. The fetcher assumes that if a branch is predicted to be taken, it
is safe to fetch down the target path.
2.9 User and Supervisor Modes
In the PowerPC Book-E architecture defines two operating states or modes,” supervisor (privileged), and user (non
privileged). The mode in which the processor is operating is controlled by MSR[PR]. When MSR[PR] is 0, the
processor is in supervisor mode and can execute all instructions and access all registers, including privileged ones.
When MSR[PR] is 1, the processor is in user mode and can only execute non privileged instructions and access
non privileged registers. An attempt to execute a privileged instruction or to access a privileged register while in
user mode causes a Privileged Instruction exception type program interrupt to occur.
Note that the name “PR” for the MSR field refers to a historical alternative name for user mode, whic is “problem
state.” Hence the value 1 in the field indicates “problem state,” and not “privileged” as one might expect. After a
reset, MSR[PR] = 0.
2.9.1 MSR Bits and Exception Handling
The current value of MSR[PR] is saved, along with all other MSR bits, in the SRR1 (for non-critical interrupts) or
SRR3 (for critical interrupts) upon any interrupt, and MSR[PR] is set to 0. Therefore, all exception handlers operate
in privileged mode.
Attempting to execute a privileged instruction while in user mode causes a privileged violation program exception
(see Program Interrupt on page 123). The PPC405 does not execute the instruction, and the program counter is
loaded with EVPR[0:15] || 0x0700, the address of an exception processing routine.
The PRR field of the Exception Syndrome Register (ESR) is set when an interrupt was caused by a privileged
instruction program exception. Software is not required to clear ESR[PPR].
2.9.2 Privileged Instructions
The instructions listed in Table 2-11 are privileged and cannot be executed in user mode.
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