AMCC PPC405 - Figure 3-3. Instruction Cache Debug Data Register (ICDBDR); ICU Debugging

80 AMCC Proprietary
Revision 1.02 - September 10, 2007
PPC405 Processor
Preliminary User’s Manual
In the following sample code, registers RN, RM, RX, and RZ are any available GPRs.
!SEQUENCE 2 Alter CCR0[DPP1, U0XE)
! Turn off interrupts
mfmsr RM
addis RZ,r0,0x0002 ! CE bit
ori RZ,RZ,0x8000 ! EE bit
andc RZ,RM,RZ ! Turn off MSR[CE,EE]
mtmsr RZ
! sync
sync
! Alter CCR0 bits
mfspr RN,CCR0 ! Read CCR0.
andi/ori RN,RN,0xXXXX ! Execute and/or function to change any CCR0 bits.
mtspr CCR0, RN ! Update CCR0.
isync ! Refetch instructions under new processor context.
! Restore MSR to original value
mtmsr RM
CCR0[CIS, CWS] do not require special programming.
3.6.2 ICU Debugging
The
icread instruction enables the reading of the instruction cache entries for the congruence class specified by
EA18:26. The cache information is read into the ICDBDR; from there it can subsequently be moved, using an
mfspr instruction, into a GPR. ICU tag information is placed into the ICDBDR as shown.
If CCR0[CIS] = 0, the data is a word of ICU data from the addressed line, specified by EA
27:29
. If CCR0[CWS] = 0,
the data is from the A-way; otherwise; the data from the B-way.
If CCR0[CIS] = 1, the cache information is the cache tag. If CCR0[CWS] = 0, the tag is from the A-way; otherwise,
the tag is from the B-way.
Programming Note: The instruction pipeline does not wait for data from an
icread instruction to arrive
before attempting to use the contents the ICDBDR. The following code sequence ensures proper results:
icread r5,r6 # read cache information
isync # ensure completion of icread
mficdbdr r7 # move information to GPR
Figure 3-3. Instruction Cache Debug Data Register (ICDBDR)
0:21 TAG Cache Tag
22:26
Reserved
27 V Cache Line Valid
Not valid
Valid
28:30
Reserved
31 LRU Least Recently Used (LRU)
A-way LRU
B-way LRU