AMCC PPC405 - Exception Vector Prefix Register (EVPR); Exception Syndrome Register (ESR); Figure 6-5. Save;Restore Register 3 (SRR3); Figure 6-6. Exception Vector Prefix Register (EVPR)

116 AMCC Proprietary
Revision 1.02 - September 10, 2007
PPC405 Processor
Preliminary User’s Manual
Because critical interrupts do not automatically clear MSR[ME], SRR2 and SRR3 can be corrupted by a machine
check interrupt, if the machine check occurs while SRR2 and SRR3 contain valid data that has not yet been saved
by the critical interrupt handler.
Because critical interrupts do not automatically clear MSR[ME], SRR2 and SRR3 can be corrupted by a machine
check interrupt, if the machine check occurs while SRR2 and SRR3 contain valid data that has not yet been saved
by the critical interrupt handler.
6.5.4 Exception Vector Prefix Register (EVPR)
The EVPR is a 32-bit register whose high-order 16 bits contain the prefix for the address of an interrupt handling
routine. The 16-bit interrupt vector offsets (shown in Table 6-2) are concatenated to the right of the high-order 16
bits of the EVPR to form the 32-bit address of an interrupt handling routine.
The contents of the EVPR can be written to a GPR using the mfspr instruction. The contents of a GPR can be
written to EVPR using the mtspr instruction.
6.5.5 Exception Syndrome Register (ESR)
The ESR is a 32-bit register whose bits help to specify the exact cause of various synchronous interrupts. These
interrupts include instruction side machine checks, data storage interrupts, and program interrupts, instruction
storage interrupts, and data TLB miss interrupts.
Instruction Machine Check Handling on page 119 describes instruction machine checks. Data Storage Interrupt on
page 120 describes data storage interrupts. Program Interrupt on page 123 describes program interrupts.
Although interrupt handling routines are not required to reset the ESR, it is recommended that instruction machine
check handlers reset the ESR; Instruction Machine Check Handling on page 119 describes why such resets are
recommended.
The contents of the ESR can be written to a GPR using the
mfspr instruction. The contents of a GPR can be
written to the ESR using the
mtspr instruction.
Figure 6-5. Save/Restore Register 3 (SRR3)
0:31 SRR3 receives a copy of the MSR when a critical
interrupt is taken; the MSR is restored from SRR3
when
rfci executes.
Figure 6-6. Exception Vector Prefix Register (EVPR)
0:15 EVP Exception Vector Prefix
16:31
Reserved
Figure 6-7. Exception Syndrome Register (ESR)
0 MCI Machine check—instruction
0 Instruction machine check did not occur.
1 Instruction machine check occurred.
1:3
Reserved