24 AMCC Proprietary
Revision 1.02 - September 10, 2007
PPC405 Processor
Preliminary User’s Manual
prioritization reduces pipeline stalls even further. When the DCU is busy with a low-priority request while a
subsequent storage operation requested by the CPU is stalled, the DCU automatically increases the priority of the
current request to the PLB.
The DCU uses a two-line flush queue to minimize pipeline stalls caused by cache misses. Line flushes are
postponed until after a line fill is completed. Registers comprise the first position of the flush queue; the line buffer
built into the output of the array for manufacturing test serves as the second position of the flush queue. Pipeline
stalls are further reduced by forwarding the requested word to the CPU during the line fill. Single-queued flushes
are non-blocking. When a flush operation is pending, the DCU can continue to access the array to determine
subsequent load or store hits. Under these conditions, load hits can occur concurrently with store hits to write-back
memory without stalling the pipeline. Requests abandoned by the CPU can also be aborted by the cache
controller.
Additional DCU features enable the programmer to tailor performance for a given application. The DCU can
function in write-back or write-through mode, as controlled by the Data Cache Write-through Register (DCWR) or
the translation look-aside buffer (TLB). DCU performance can be tuned to balance performance and memory
coherency. Store-without-allocate, controlled by the SWOA field of the Core Configuration Register 0 (CCR0), can
inhibit line fills caused by store misses to further reduce potential pipeline stalls and unwanted external bus traffic.
Similarly, load-without-allocate, controlled by CCR0[LWOA], can inhibit line fills caused by load misses.
1.4.2 Memory Management Unit
The 4GB address space of the PPC405 is presented as a flat address space.
The MMU provides address translation, protection functions, and storage attribute control for embedded
applications. The MMU supports demand paged virtual memory and other management schemes that require
precise control of logical to physical address mapping and flexible memory protection. Working with appropriate
system level software, the MMU provides the following functions:
• Translation of the 4GB logical address space into physical addresses
• Independent enabling of instruction and data translation/protection
• Page level access control using the translation mechanism
• Software control of page replacement strategy
• Additional control over protection using zones
• Storage attributes for cache policy and speculative memory access control
The MMU can be disabled under software control. If the MMU is not used, the PPC405 provides other storage
control mechanisms.
The translation lookaside buffer (TLB) is the hardware resource that controls translation and protection. It consists
of 64 entries, each specifying a page to be translated. The TLB is fully associative; a page entry can be placed
anywhere in the TLB. The translation function of the MMU occurs pre-cache for data accesses. Cache tags and
indexing use physical addresses for data accesses; instruction fetches are virtually indexed and physically tagged.
Software manages the establishment and replacement of TLB entries. This gives system software significant
flexibility in implementing a custom page replacement strategy. For example, to reduce TLB thrashing or
translation delays, software can reserve several TLB entries for globally accessible static mappings. The
instruction set provides several instructions to manage TLB entries. These instructions are privileged and require
the software to be executing in supervisor state. Additional TLB instructions are provided to move TLB entry fields
to and from GPRs.
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