AMCC Proprietary 355
Revision 1.02 - September 10, 2007
PPC405 Processor
Preliminary User’s Manual
10.6 Time Base Registers
The PowerPC Architecture provides a 64-bit time base. Timer Facilities on page 129 describes the architected time
base. In the PPC405, the time base is implemented as two 32-bit time base registers (TBRs). The low-order 32 bits
of the time base are read from the TBL and the high-order 32 bits are read from the TBL.
User-mode access to the TBRs is read-only, and there is no explicitly privileged read access to the time base.
The
mftb instruction reads from TBL and TBU. (Writing the time base is accomplished by moving the contents of a
GPR to a pair of SPRs, which are also called TBL and TBU, using the
mtspr instruction.)
Table 10-4 shows the mnemonics, names, and numbers of the TBRs. The columns under “TBRN” list the register
numbers used as operands in assembler language coding of the
mftb and mtspr instructions. The column labeled
“TBRF” lists the corresponding fields contained in the machine code of
mftb and mtspr. The TBRN field contains
two five-bit subfields of the TBRF field; the subfields are reversed in the machine code for the mftb and mtspr
instructions (TBRN ← TBRF
5:9
|| TBRF
0:4
). Note that the assembler handles the special coding transparently.
PVR Processor Version Register 0x11F 0x3E8 Read-only 39
SGR Storage Guarded Register 0x3B9 0x33D Read/Write 107
SLER Storage Little Endian Register 0x3BB 0x37D Read/Write 107
SPRG0 SPR General 0 0x110 0x208 Read/Write 39
SPRG1 SPR General 1 0x111 0x228 Read/Write 39
SPRG2 SPR General 2 0x112 0x248 Read/Write 39
SPRG3 SPR General 3 0x113 0x268 Read/Write 39
SPRG4 SPR General 4 0x104 0x088 Read-only 39
SPRG4 SPR General 4 0x114 0x288 Read/Write 39
SPRG5 SPR General 5 0x105 0x0A8 Read-only 39
SPRG5 SPR General 5 0x115 0x2A8 Read/Write 39
SPRG6 SPR General 6 0x106 0x0C8 Read-only 39
SPRG6 SPR General 6 0x116 0x2C8 Read/Write 39
SPRG7 SPR General 7 0x107 0x0E8 Read-only 39
SPRG7 SPR General 7 0x117 0x2E8 Read/Write 39
SRR0 Save/Restore Register 0 0x01A 0x340 Read/Write 115
SRR1 Save/Restore Register 1 0x01B 0x360 Read/Write 115
SRR2 Save/Restore Register 2 0x3DE 0x3DE Read/Write 115
SRR3 Save/Restore Register 3 0x3DF 0x3FE Read/Write 115
SU0R Storage User-defined 0 Register 0x3BC 0x39D Read/Write 105
TBL Time Base Lower 0x11C 0x388 Write-only 130
TBU Time Base Upper 0x11D 0x3A8 Write-only 130
TCR Timer Control Register 0x3DA 0x35E Read/Write 135
TSR Timer Status Register 0x3D8 0x31E Read/Clear 135
USPRG0 User SPR General 0 0x100 0x008 Read/Write 39
XER Fixed Point Exception Register 0x001 0x020 Read/Write 37
ZPR Zone Protection Register 0x3B0 0x21D Privileged 103
Table 10-3. Special Purpose Registers (Continued)
Mnemonic Register Name SPRN SPRF Access
See
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