AMCC Proprietary 131
Revision 1.01 - February 19, 2007
PPC405 Processor
Preliminary User’s Manual
7.1.1 Reading the Time Base
The following code provides an example of reading the time base. mftb moves the low-order 32 bits of the time
base to a GPR; mftbu moves the high-order 32 bits of the time base to a second GPR.
loop:
mftbu Rx # load from TBU
mftb Ry # load from TBL
mftbu Rz # load from TBU
cmpw Rz, Rx # see if old = new
bne loop # loop/reread if rollover occurred
The comparison and loop ensure that a consistent pair of values is obtained.
7.1.2 Writing the Time Base
The following code provides an example of writing the time base. Writing the time base is privileged. mttbl moves
the contents of a GPR to the low-order 32 bits of the time base; mttbu moves the contents of a second GPR to the
high-order 32 bits of the time base.
lwz Rx, upper # load 64-bit time base value into Rx and Ry
lwz Ry, lower
li Rz, 0
mttbl Rz # force TBL to 0 to avoid rollover while writing TBU
mttbu Rx # set TBU
mttbl Ry # set TBL
7.2 Programmable Interval Timer (PIT)
The PIT is a 32-bit SPR that decrements at the same rate as the time base. The PIT is read and written using
mfspr and mtspr, respectively. Writing to the PIT also simultaneously writes to a hidden reload register. Reading
the PIT using mfspr returns the current PIT contents; the hidden reload register cannot be read. When a non-zero
value is written to the PIT, it begins to decrement. A PIT event occurs when a decrement occurs and the PIT count
is set to 1. When a PIT event occurs, the following occurs:
1. If the PIT is in auto-reload mode (the ARE field of the Timer Control Register (TCR) is 1), the PIT is loaded with
the last value an mtspr wrote to the PIT. A decrement from a PIT count of 1 immediately causes a reload; no
intermediate PIT content of 0 occurs.
If the PIT is not in auto-reload mode (TCR[ARE] = 0), a decrement from a PIT count of 1 simply causes a PIT
content of 0.
2. TSR[PIS] is set to 1.
3. If enabled (TCR[PIE] = 1 and the EE field of the Machine State Register (MSR) is 1), a PIT interrupt is taken.
See “Programmable Interval Timer (PIT) Interrupt” on page 10-44 for details of register behavior during a PIT
interrupt.
The interrupt handler should use software to reset the PIS field of the Timer Status Register (TSR). This is done by
using mtspr to write a word to the TSR having a 1 in TSR[PIS] and any other bits to be cleared, and a 0 in all other
bits. The data written to the TSR is not direct data, but a mask. A 1 clears a bit; a 0 has no effect.
Using mtspr to force the PIT to 0 does not cause a PIT interrupt. However, decrementing that was ongoing at the
instant of the mtspr instruction can cause the appearance of an interrupt. To eliminate the PIT as a source of inter-
rupts, write a 0 to TCR[PIE], the PIT interrupt enable bit.
To eliminate all PIT activity:
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