102 AMCC Proprietary
Revision 1.02 - September 10, 2007
PPC405 Processor
Preliminary User’s Manual
5.7 Access Protection
The PPC405 provides virtual-mode access protection. The TLB entry enables system software to control general
access for programs in the problem state, and control write and execute permissions for all pages. The TLB entry
can specify zone protection that can override the other access control mechanisms supported in the TLB entries.
TLB entry and zone protection methods also support access controls for cache operation and string loads/stores.
5.7.1 Access Protection Mechanisms in the TLB
For MMU access protection to be in effect, one or both of MSR[IR] or MSR[DR] must be set to one to enable
address translation. MSR[IR] enables protection on instruction fetches, which are inherently read-only. MSR[DR]
enables protection on data accesses (loads/stores).
5.7.1.1 General Access Protection
The translation ID (TLB_entry[TID]) provides the first level of MMU access protection. This 8-bit field, if non-zero, is
compared to the contents of TLB_entry[PID]. These fields must match in a valid TLB entry if any access is to be
allowed. In typical use, it is assumed that a program in the supervisor state, such as a real-time operating system,
sets the process ID (PID) before starting a problem state program that is subject to access control.
If TLB_entry[TID] = 0x00, the associated memory page is accessible to all programs, regardless of their PID. This
enables multiple processes to share common code and data. The common area is still subject to all other access
protection mechanisms. Figure 5-4 illustrates the Process ID Register.
5.7.1.2 Execute Permissions
If instruction address translation is enabled, instruction fetches are subject to MMU translation and have MMU
access protection. Fetches are inherently read-only, so write protection is not needed. Instead, using
TLB_entry[EX], a memory page is marked as executable (contains instructions) or not executable (contains only
data or memory-mapped control hardware).
If an instruction is pre-fetched from a memory page for which TLB_entry[EX] = 0, the instruction is tagged as an
error. If the processor subsequently attempts to execute this instruction, an instruction storage interrupt results.
This interrupt is precise with respect to the attempted execution. If the fetcher discards the instruction without
attempting to execute it, no interrupt will result.
Zone protection can alter execution protection.
5.7.1.3 Write Permissions
If MSR[DR] = 1, data loads and stores are subject to MMU translation and are afforded MMU access protection.
The existence of a TLB entry describing a memory page implies read access; write access is controlled by
TLB_entry[WR].
If a store (including those caused by dcbz, dcbi, or dccci) is made to an EA having TLB_entry[WR] = 0, a data
storage interrupt results. This interrupt is precise.
Figure 5-4. Process ID (PID)
0:23 Reserved
24:31 Process ID
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