AMCC Proprietary 101
Revision 1.02 - September 10, 2007
PPC405 Processor
Preliminary User’s Manual
5.5.2 TLB Read/Write Instructions (tlbre/tlbwe)
TLB entries can be accessed for reading and writing by tlbre and tlbwe, respectively. Separate extended
mnemonics are available for the TLBHI (tag) and TLBLO (data) portions of a TLB entry.
5.5.3 TLB Invalidate Instruction (tlbia)
tlbia sets TLB_entry[V] = 0 to invalidate all TLB entries. All other TLB entry fields remain unchanged.
Using tlbwe to set TLB_entry[V] = 0 invalidates a specific TLB entry.
5.5.4 TLB Sync Instruction (tlbsync)
tlbsync guarantees that all TLB operations have completed for all processors in a multi-processor system.
PPC405 provides no multiprocessor support, so this instruction performs no function. The instruction is included to
facilitate code portability.
5.6 Recording Page References and Changes
When system software manages virtual memory, the software views physical memory as a collection of pages.
Each page is associated with at least one TLB entry. To manage memory effectively, system software often must
know whether a particular page has been referenced or modified. Note that this involves more than knowing
whether a particular TLB entry was used to reference or alter memory, because multiple TLB entries can translate
to the same page.
When system software manages a demand-paged environment, and the software needs to replace the contents of
a page with other data, previously referenced pages (accessed for any purpose) are more likely to be maintained
than pages that were never referenced. If the contents of a page must be replaced, and data contained in that page
was modified, system software generally must write the contents of the modified page to the backing store before
replacing its contents. System software must maintain records to control the environment.
Similarly, when system software manages TLB entries, the software often must know whether a particular TLB
entry was referenced. When the system software must select a TLB entry to cast out, previously referenced entries
are more likely to be maintained than entries which were never referenced. System software must also maintain
records for this purpose.
The PPC405 does not provide hardware reference or change bits, but TLB miss interrupts and data storage
interrupts enable system software to maintain reference information for TLB entries and their associated pages,
respectively.
A possible algorithm follows. First, the TLB entries are built, with each TLB_entry[V, WR] = 0. System software
retains the index and EPN of each entry.
The first attempt by application code to access a page causes a TLB miss interrupt, because its TLB entry is
marked invalid. The TLB miss handler records the reference to the TLB entry (and to the associated page) in a
data structure, then sets TLB_entry[V] = 1. (Note that TLB_entry[V] can be considered a reference bit for the TLB
entry.) Subsequent read accesses to the page associated with the TLB entry proceed normally.
In the example just given for recording TLB entry references, the first write access to the page using the TLB entry,
after the entry is made valid, causes a data storage interrupt because write access was turned off. The TLB miss
handler records the write to the page in a data structure, for use as a “changed” flag, then sets TLB_entry[WR] = 1
to enable write access. (Note that TLB_entry[WR] can be considered a change bit for the page.) Subsequent write
accesses to the page proceed normally.
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