AMCC Proprietary 75
Revision 1.02 - September 10, 2007
PPC405 Processor
Preliminary User’s Manual
For cacheable memory, the store without allocate (SWOA) field of the CCR0 controls the type of store resulting
from a store miss. If CCR0[SWOA] = 0, a store miss causes a line fill. If CCR0[SWOA] = 1, store misses do not
result in a line fill, but in a single word store to external memory.
3.4.4 Data Cachability Control
When data address translation is disabled (MSR[DR] = 0), data cachability is controlled by the Data Cache
Cachability Register (DCCR). Each bit in the DCCR (DCCR[S0:S31]) controls the cachability of a 128MB region
(see Real-Mode Storage Attribute Control on page 105). If DCCR[Sn] = 1, caching is enabled for the specified
region; otherwise, caching is inhibited.
When data address translation is enabled (MSR[DR] = 1), data cachability is controlled by the I bit in the TLB entry
for the memory page. If TLB_entry[I] = 1, caching is inhibited; otherwise caching is enabled. Cachability is
controlled separately for each page, which can range in size from 1KB to 16MB. Translation Lookaside Buffer
(TLB) on page 92 describes the TLB.
Programming Note: The PowerPC Architecture does not support memory models in which write-through is
enabled and caching is inhibited.
The performance of the PPC405 is significantly lower while accessing memory in cache-inhibited regions.
Following system reset, address translation is disabled and all DCCR bits are reset to 0 so that no memory regions
are cacheable. The dccci instruction must execute 256 times before regions can be designated as cacheable. This
invalidates all congruence classes before enabling the cache. Address translation can then be enabled, if required,
and the TLB or the DCCR can then be configured for the desired cachability.
Programming Note: If a data block corresponding to the effective address (EA) exists in the cache, but the
EA is non cacheable, loads and stores (including dcbz) to that address are considered programming errors
(the cache block should previously have been flushed). The only instructions that can legitimately access such
an EA in the data cache are the cache management instructions dcbf, dcbi, dcbst, dcbt, dcbtst, dccci, and
dcread.
3.4.5 DCU Coherency
The DCU does not provide snooping. Application programs must carefully use cache-inhibited regions and cache
control instructions to ensure proper operation of the cache in systems where external devices can update
memory.
3.5 Cache Instructions
For detailed descriptions of the instructions described in the following sections, see Instruction Set on page 157
In the instruction descriptions, the term “block” is synonymous with cache line. A block is the unit of storage
operated on by all cache block instructions.
3.5.1 ICU Instructions
The following instructions control instruction cache operations:
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