72 AMCC Proprietary
Revision 1.02 - September 10, 2007
PPC405 Processor
Preliminary User’s Manual
(EA
19:29
) overlap the translated RA bits. For 1KB pages, overlap in EA
19:21
and RA
19:21
could result in as many as
8 synonyms. In other words, data from the same RA could occur as many as 8 locations in the cache array.
Similarly, for 4KB pages, EA
0:19
are translated. Differences in EA
19
and RA
19
could result in as many as 2
synonyms. For the next largest page size (16KB), only EA
0:17
are translated. Because there is no overlap with
index bits EA
19:21
, synonyms do not occur.
In practice, cache synonyms occur when a real instruction page having multiple virtual mappings exists in multiple
cache lines. For 1KB pages, all EAs differing in EA
19:21
must be cast out of cache, using an icbi instruction for each
such EA (up to eight per cache line in the page). For 4KB pages, all EAs differing in EA19 must be cast out in the
same manner (up to two per cache line in the page). For larger pages, cache synonyms do not occur, and casting
out any of the multiple EAs removes the physical information from the cache.
Programming Note: To prevent the occurrence of cache synonyms, use only page sizes greater than the
cache way size (8KB), if possible. For the PPC405, the minimum such page size is 16KB.
3.3.4 ICU Coherency
The ICU does not “snoop” external memory or the DCU. Programmers must follow special procedures for ICU
synchronization when self-modifying code is used or if a peripheral device updates memory containing instructions.
The following code example illustrates the necessary steps for self-modifying code. This example assumes that
addr1 is both data and instruction cacheable.
stw regN, addr1 # the data in regN is to become an instruction at addr1
dcbst addr1 # forces data from the data cache to memory
sync # wait until the data actually reaches the memory
icbi addr1 # the previous value at addr1 might already be in
the instruction cache; invalidate it in the cache
isync # the previous value at addr1 may already have been
pre-fetched into the queue; invalidate the queue
so that the instruction must be re-fetched
3.4 DCU Organization
The DCU manages data transfers between external cacheable memory and the general-purpose registers in the
execution unit.
The DCU contains a two-way set-associative 16KB cache memory. Each way is organized in 256 lines of eight
words (32 bytes) each.
As shown in Table 3-2, tag ways A and B store data address bits A0:19 for each line in cache ways A and B. Data
address bits A18:26 serve as the index to the cache array. The two cache lines that correspond to the same line
index (one in each way) are called a congruence class.
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