AMCC Proprietary 432
Revision 1.02 - September 10, 2007
PPC405 Processor
Preliminary User’s Manual
C.2.2 Branches
Branch instructions are decoded in prefetch buffer 0 (PFB0) and the decode stage of the instruction pipeline.
Branch targets, whether the branch is known or predicted taken, can be fetched from the PFB0 and DCD stages.
Incorrectly predicted branches can be corrected from the DCD or EXE (execute) stages of the pipeline.
Branches can be known taken or known not taken, or can have address or condition dependencies. Branches
having address dependencies are never predicted taken. The directions of conditional branches having no address
dependencies are statically predicted.
Conditional branches may depend on the results of an instruction that is changing the CR or the CTR.
Address dependencies can occur when:
•A
bclr instruction that is known taken, or unresolved, follows (immediately, or separated by only one instruc-
tion) a link updating instruction (
mtlr or a branch and link).
•A
bcctr instruction that is known taken, or unresolved, follows (immediately, or separated by only one instruc-
tion) a counter updating instruction (
mtctr or a branch that decrements the counter).
Instruction timings for branch instructions follow:
• A branch known not taken (BKNT) executes in one clock cycle. By definition a BKNT does not have address or
condition dependencies.
• A branch known taken (BKT) by definition has no condition dependencies, but can have address dependen-
cies.A BKT without address dependencies can execute in one clock cycle if it is first decoded from the PFB0
stage, or in two clock cycles if it is first decoded in the DCD stage. A BKT having address dependencies can
execute in two clock cycles if there is one instruction between the branch and the address dependency, or in
three clock cycles if there are no instructions between the branch and address dependency.
• A branch predicted not taken (BPNT), which must have condition dependencies, executes in one clock cycle if
the prediction is correct. If the prediction is incorrect, the branch can take two or three cycles. If there was one
instruction between the branch and the instruction causing the condition dependency, the branch executes in
two cycles. If there were no instructions between the branch and the instruction causing the condition depen-
dency, the branch executes in three clock cycles.
• A branch that is correctly predicted taken (BPT), which must have condition dependencies, executes in one
clock cycle, if it is first decoded from the PFB0 stage, or two clock cycles if it is first decoded in the DCD stage.
If the prediction is incorrect, the branch can take two or three cycles. If there is one instruction between the
branch and the instruction causing the condition dependency, the branch executes in two cycles. If there are
no instructions between the branch and the instruction causing the condition dependency, the branch executes
in three clock cycles.
C.2.3 Multiplies
For multiply instructions having two word operands, hardware internal to the core automatically detects smaller
operand sizes (by examining sign bit extension) to reduce the number of cycles necessary to complete the
multiplication.
The PPC405 also supports multiply accumulate (MAC) instructions and multiply instructions having halfword
operands.
Word and halfword multiply instructions are pipelined in the execution unit and use the same multiplication
hardware. Because these instructions are pipelined in the execution stage they have latency and reissue rate cycle
numbers. Under conditions to be described, a second multiply or MAC instruction can begin execution before the
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