AMCC Proprietary 87
Revision 1.02 - September 10, 2007
PPC405 Processor
Preliminary User’s Manual
The following description applies only to applications that alias the OCM address space and perform a mix of data-
side loads and stores. It does not apply to applications that use data-side stores only to initialize OCM with
instructions.
If a data-side OCM store is followed in the next cycle by a data-side load, the load actually accesses the OCM
array before the store. This is due to the nature of the processor pipeline, the cycle availability of the store data,
and the fact that data-side loads have a higher priority than data-side stores. In this scenario, store data is queued
in a register while the load accesses the array. Further, if the store is immediately followed by a sequence of
consecutive loads, it remains in the queue until the last of the consecutive loads has accessed the OCM array. The
queued store data is written into the OCM array in the first cycle that does not have a data-side load operation
accessing the array.
Consider a scenario where such a situation causes store data to be held in the store data queue. If any of the loads
access the same address as the address of the store operation whose data is being held in the store data queue,
there is a need to bypass the store data from the store data queue to provide the correct data to the load operation.
A bypass is determined to be required by comparing the pending store address with the load address. However,
the comparison is done with a 16KB address representation for the load and store operations, not the 4KB address
(the physical size of the PPC405 OCM array). If the 16KB address compares, the store data is bypassed to the
load operation. This implies that a bypass results for address aliasing only when the OCM addresses match at a
16KB multiple, which corresponds to a match of address bits 18:29 (a word address that is further specified by byte
enables). Although the physical address space is aliased at 4KB multiples, the bypass determination is made at
16KB multiples. Therefore, if bits 18:19 of an aliased load address do not match bits 18:19 of the 16KB store
address of the data being held in the store data queue, the load data will not be coherent. Instead of returning the
most recently stored data, which is being held in the store data queue, the load returns “old” data previously stored
in and accessed from the OCM array.
Table 4-1 provides examples that describe bypass behavior when address aliasing is used.
Example 1 provides the most basic example, in which the load and store addresses are the same. This results in
the load accessing the queued store data, bypassing the OCM array to satisfy the load.
Example 2 shows two different addresses that are not aliased (both addresses are in the 4KB SRAM address
space). No bypass occurs, and the load returns the correct data from the OCM array.
Examples 3 and 4 show aliased addresses that do not bypass data because the addresses do not compare within
a 16KB address space. In both examples, address bits 18:19 do not match. In both examples, the load does not
return the most recently stored data from the store data queue; the load returns the “old’ data from the array. To
avoid such problems, alias on 16KB boundaries. If addresses are aliased on 4KB boundaries, place at least one
instruction that does not access the data-side OCM between a load and a store to the same aliased address so the
store data has a cycle to be written into the array.
Table 4-1. Examples of Store Data Bypass
Example Store Address Load Address 4KB Aliased Address 16KB Aliased Address Bypass
1 0x00000100 0x00000100 Same Same Yes
2 0x00000100 0x00000400 No No No
3 0x00000100 0x00001100 Yes No, loads old data No
4 0x00000100 0x00005100 Yes No, loads old data No
5 0x00000100 0x00004100 Yes Yes Yes
6 0x00000100 0x00008100 Yes Yes Yes
To Next Page
Loading...