AMCC PPC405 - Table 9-10. Extended Mnemonics for Cmp

AMCC Proprietary 188
Revision 1.02 - September 10, 2007
PPC405 Processor
cmp
Compare
Preliminary User’s Manual
cmp
Compare
c
0:3
←
4
0
if (RA) < (RB) then c
0
← 1
if (RA) > (RB) then c
1
← 1
if (RA) = (RB) then c
2
← 1
c
3
← XER[SO]
n
← BF
CR[CRn] ← c
0:3
The contents of register RA are compared with the contents of register RB using a 32-bit signed compare.
The CR field specified by the BF field is updated to reflect the results of the compare and the value of XER[SO] is
placed into the same CR field.
If instruction bit 31 contains 1, the contents of CR[CR0] are undefined.
Registers Altered
• CR[CRn] where n is specified by the BF field
Invalid Instruction Forms
• Reserved fields
Programming Note
The PowerPC Architecture defines this instruction as cmp BF,L,RA,RB, where L selects operand size for 64-bit
PowerPC implementations. For all 32-bit PowerPC implementations, L = 0 is required (L = 1 is an invalid form);
hence for PPC405, use of the extended mnemonic cmpw BF,RA,RB is recommended.
Architecture Note
This instruction is part of the PowerPC User Instruction Set Architecture.
cmp BF, 0, RA, RB
31 BF
RA RB 0
069111621 31
Table 9-10. Extended Mnemonics for cmp
Mnemonic Operands Function
Other Registers
Altered
cmpw [BF,] RA, RB
Compare Word; use CR0 if BF is omitted.
Extended mnemonic for
cmp BF,0,RA,RB