AMCC Proprietary 97
Revision 1.02 - September 10, 2007
PPC405 Processor
Preliminary User’s Manual
5.3.4 Shadow Data TLB
To enhance performance, eight data-side TLB entries are kept in a eight-entry fully-associative shadow array. This
array, called the data TLB (DTLB), helps to avoid TLB contention between instruction accesses to the TLB and
load/store operations. Replacement and invalidation of the DTLB entries is managed by hardware. See “Shadow
TLB Consistency” on page 97 for details.
The DTLB can be considered a level-1 data-side TLB; the UTLB serves as the level-2 data-side TLB. The DTLB is
used only during instruction execute for storing data address translations. Each DTLB entry contains the
translation information for a page. The processor uses the DTLB for address translation of data accesses when
MSR[DR] = 1.
5.3.4.1 1 DTLB Accesses
The execute unit accesses the DTLB independently of the rest of the MMU. DTLB accesses are transparent to the
executing program, except that DTLB hits contribute to higher overall instruction throughput by allowing instruction
address translations to occur in parallel. Therefore, when data accesses hit in the DTLB, the address translation
mechanisms in the UTLB are available for use by instruction accesses simultaneously.
The DTLB requests a new entry from the UTLB when a DTLB miss occurs. A three-cycle latency occurs at each
DTLB miss that is also a UTLB hit; the latency is longer if it is also a UTLB miss. If there is contention for the UTLB
from the instruction side, the data side has priority. A round-robin replacement algorithm replaces existing entries
with new entries.
5.3.5 Shadow TLB Consistency
To help maintain the integrity of the shadow TLBs, the processor invalidates the ITLB and DTLB contents when the
following context-synchronizing events occur:
• isync instruction
• Processor context switch (all interrupts, rfi, rfci)
• sc instruction
If software updates a translation/protection mechanism (UTLB, PID, ZPR, or MSR) and must synchronize these
updates with the ITLB and DTLB, the software must perform the necessary context synchronization.
A typical example is the manipulation of the TLB by an operating system within an interrupt handler for a TLB miss.
Upon entry to the interrupt handler, the contents of the ITLB and DTLB are invalidated and translation is disabled.
If the operating system simply made the TLB updates and returned from the handler (using rfi or rfci), no
additional explicit software action would be required to synchronize the ITLB and DTLB.
If, instead, the operating system enables translation within the handler and then performs TLB updates within the
handler, those updates would not be effective in the ITLB and DTLB until rfi or rfci is executed to return from the
handler. For those TLB updates to be reflected in the ITLB and DTLB within the handler, an isync must be issued
after TLB updates finish. Failure to properly synchronize the shadow TLBs can cause unexpected behavior.
Programming Note: As a rule of thumb, follow software manipulation of an translation mechanism (if
performed while translation is active) with a context-synchronizing operation (usually isync).
Figure 5-3 illustrates the relationship of the shadow TLBs and UTLB in address translation:
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