AMCC Proprietary 85
Revision 1.02 - September 10, 2007
PPC405 Processor
Preliminary User’s Manual
4. On-Chip Memory (OCM)
The on-chip memory (OCM) subsystem consists of a memory controller that connects the PPC405 processor core
to an SRAM array. OCM is ideal for applications requiring low latency access to critical instructions and data. OCM
can provide performance that is identical to cache hits, yet, unlike a cache, the OCM never misses. Instructions
and data stored in the OCM are always available because OCM contents only change under program control.
Therefore, if the programmer avoids instruction-side and data-side OCM access contention, OCM can provide
information availability that is superior to a cache line locking scheme. OCM is superior because it can provide
single cycle performance identical to cache hits without locking down portions of the cache. This results in more
effective cache utilization for the processor.
Instructions and data returned from OCM interface do not flow through the PPC405 CPU caches. The caches
remain available for caching from other memory sources accessed across the PLB interface. The system designer
must ensure that each address has a single access path into the PPC405 CPU for a given software process. Each
address that is requested should be found in either the OCM address space or the PLB address space, but not in
both.
Code to initialize OCM should execute in non-OCM address space in a region marked as non cacheable. The
initialization code should invalidate the cache arrays (in the ICU and DCU, as appropriate) to ensure that no
addresses to be programmed as OCM space are in the cache. After programming the OCM address and control
registers, the OCM address space should remain marked as non-cacheable.
Read and write accesses to the OCM array share a single access port. OCM accesses have the following
priorities:
1. Data-side OCM reads (loads)
2. Data-side OCM writes (stores)
3. Instruction-side OCM read (fetches)
Data-side OCM reads occur in one cycle. Data-side writes also complete in one cycle, though they can be
preempted by higher priority data-side reads. Instruction-side OCM reads occur by default (that is, after a reset) in
two cycles. However, when the Instruction-Side Two-Cycle Mode field of the OCM Instruction-Side Control
Register (if it exists) is set to 0, instruction-side OCM reads occur in one cycle, unless preempted by higher priority
data-side transfers. Two-cycle mode is provided for chips that cannot make instruction-side timing to the processor
core. The PPC405 processor core, however, meets the timing requirement. Therefore, programmers should set the
OCM Instruction-Side Control Register (if it exists) to 0 during chip initialization.
The OCM can also transfer data between the PLB and internal SRAM.
The OCM has the following features:
• Supports two non-overlapping memory banks configurable as 16 KB
• Simultaneous PLB, Instruction-side OCM and Data-side OCM access
• PLB3 slave cycles support the following
- 64 bit slave attachment addressable by any PLB master
- Single-beat read and write (1 to 8 bytes)
- 4-, 8- and 16-word line read and write
- Doubleword and word read and write bursts
- Slave-terminated doubleword and word bursts
- Master-terminated variable-length bursts
- Data parity generation and checking
- Read/Write protection per bank
• Instruction-side interface supports the following data parity checking
• Data-side interface supports the following:
- 1-wait state OCM access with 1-deep write buffer
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