AMCC PPC405 - C.2.4 Scalar Load Instructions

AMCC Proprietary 433
Revision 1.02 - September 10, 2007
PPC405 Processor
Preliminary User’s Manual
first multiply or MAC instruction completes. When these conditions are met, the reissue rate cycle numbers should
be used; otherwise, the latency cycle numbers should be used. (A MAC or multiply instruction can follow another
MAC or a multiply and still meet the conditions that support the use of the reissue rate cycle numbers.
Use reissue rate cycle numbers for multiply or MAC instructions that are followed by another multiply or MAC
instruction, and do not have an operand dependency from a previous multiply or MAC instruction. However, one
operand dependency is allowed for reissue rate cycle numbers. Internal forwarding logic allows the accumulate
value of a first MAC instruction to be used as the accumulate value of a second MAC instruction without affecting
the reissue rate.
Use latency cycle numbers for multiply or MAC instructions that are not followed by another multiply or MAC, or
that have an operand dependency from a previous multiply or MAC instruction. However, accumulate-only
dependencies between adjacent MAC instructions use reissue rate cycle numbers.
An operand dependency exists when a second multiply or MAC instruction depends on the result of a first multiply
or MAC instruction.
Table C-1 summarizes the multiply and MAC instruction timings. In the table, the syntax “[
o]” indicates that the
instruction has an “o” form that updates XER[SO,OV], and a “non-o” form. The syntax “[
.]” indicates that the
instruction has a “record” form that updates CR[CR0], and a “non-record” form.
C.2.4 Scalar Load Instructions
Generally, the PPC405 executes cacheable load instructions that hit in the data cache array or line fill buffer, or
non cacheable load instructions that hit in the line fill buffer (when enabled), in one cycle. However, the pipelined
nature of load instructions can even cause loads that hit in the cache or line fill buffer to appear to take extra cycles
under some conditions.
If a load is followed by an instruction that uses the load target as an operand, a load-use dependency exists. When
the load target is returned, it is forwarded to the operand register of the “using” instruction. This forwarding results
in an additional cycle of latency to a load immediately followed by a “using” instruction, causing the load to appear
to execute in two cycles.
Because the PPC405 can execute instructions that follow load misses if no load-use dependency exists, the load
and the “using” instruction should be separated by two “non-using” instructions when possible. If only one
instruction can be placed between the load and the “using” instruction, the load appears to execute in two cycles.
Table C-1. Multiply and MAC Instruction Timing
Operation Reissue Rate Cycles Latency Cycles
MAC
MAC and negative MAC instructions
12
Halfword x Halfword
mullhw[.], mullhwu[.], mulhhw[.], mulhhwu[.],
mulchw[.], mulchwu[.]
12
mulli
[.], mullw[o][.],
mulhw[.], mulhwu[.]
23
Halfword x Word
mulli
[.], mullw[o][.],
mulhw[.], mulhwu[.]
23
Word
× Word
mullw
[o][.], mulhw[.], mulhwu[.]
45