AMCC PPC405 - Alignment Interrupt; Program Interrupt; Table 6-10. Alignment Interrupt Summary; Table 6-11. Register Settings During Alignment Interrupts

AMCC Proprietary 123
Revision 1.02 - September 10, 2007
PPC405 Processor
Preliminary User’s Manual
6.11 Alignment Interrupt
Alignment interrupts are caused by dcbz instructions to non cacheable or write-through storage and misaligned
dcread, lwarx, or stwx. instructions. Table 6-10 summarizes the instructions and conditions causing alignment
interrupts.
Execution of an instruction causing an alignment interrupt is prohibited from completing. SRR0 is written with the
address of that instruction and the current contents of the MSR are saved into SRR1. The DEAR is written with the
address that caused the alignment error. The MSR bits are written with the values shown in Table 6-11. The high-
order 16 bits of the program counter are written with the contents of the EVPR and the low-order 16 bits of the
program counter are written with 0x0600. Interrupt processing begins at the new address in the program counter.
Executing an rfi instruction restores the program counter from SRR0 and the MSR from SRR1, and execution
resumes at the address in the program counter.
Alignment interrupts cannot be disabled. To avoid overwrites of SRR0 and SRR1 by alignment interrupts that occur
within a handler, interrupt handlers should save these registers as soon as possible.
6.12 Program Interrupt
Program interrupts are caused by attempting to execute:
• An illegal instruction
• A privileged instruction while in the problem state
• Executing a trap instruction with conditions satisfied
The ESR bits that differentiate these situations are listed and described in Table 6-12. When a program interrupt
occurs, the appropriate bit is set and the others are cleared. These interrupts are not maskable.
Table 6-10. Alignment Interrupt Summary
Instructions Causing Alignment Interrupts Conditions
dcbz
EA in non cacheable or write-through storage
dcread, lwarx, stwcx. EA not word-aligned
Table 6-11. Register Settings during Alignment Interrupts
SRR0 Written with the address of the instruction causing the alignment interrupt
SRR1 Written with the contents of the MSR
PC EVPR[0:15] || 0x0600
DEAR Written with the address that caused the alignment violation
Table 6-12. ESR Usage for Program Interrupts
Bits Interrupts Cause
ESR[PIL] Illegal instruction Opcode not recognized
ESR[PPR] Privileged instruction Attempt to use a privileged instruction in the problem state