AMCC PPC405 - Page 4

4 AMCC Proprietary
Revision 1.02 - September 10, 2007
PPC405 Processor
Preliminary User’s Manual
2.3.4 The Time Base ................................................................................................................................ 41
2.3.5 Machine State Register (MSR) ........................................................................................................ 42
2.3.6 Device Control Registers ................................................................................................................. 42
2.4 Data Types and Alignment ................................................................................................................... 42
2.4.1 Alignment for Storage Reference and Cache Control Instructions .................................................. 43
2.4.2 Alignment and Endian Operation .................................................................................................... 43
2.4.3 Summary of Instructions Causing Alignment Exceptions ................................................................ 43
2.5 Byte Ordering ............................................................................................................................................ 44
2.5.1 Structure Mapping Examples .......................................................................................................... 44
2.5.1.1 Big Endian Mapping ................................................................................................................. 45
2.5.1.2 Little Endian Mapping .............................................................................................................. 45
2.5.2 Support for Little Endian Byte Ordering ........................................................................................... 45
2.5.3 Endian (E) Storage Attribute ........................................................................................................... 46
2.5.3.1 Fetching Instructions from Little Endian Storage Regions ....................................................... 46
2.5.3.2 Accessing Data in Little Endian Storage Regions .................................................................... 47
2.5.3.3 PowerPC Byte-Reverse Instructions ........................................................................................ 47
2.6 Instruction Processing .............................................................................................................................. 49
2.7 Branch Processing .................................................................................................................................... 50
2.7.1 Unconditional Branch Target Addressing Options .......................................................................... 50
2.7.2 Conditional Branch Target Addressing Options .............................................................................. 50
2.7.3 Conditional Branch Condition Register Testing ............................................................................... 51
2.7.4 BO Field on Conditional Branches .................................................................................................. 51
2.7.5 Branch Prediction ............................................................................................................................ 52
2.8 Speculative Accesses ............................................................................................................................... 53
2.8.1 Speculative Accesses in the PPC405 ............................................................................................. 53
2.8.1.1 Prefetch Distance Down an Unresolved Branch Path ............................................................. 54
2.8.1.2 Prefetch of Branches to the CTR and Branches to the LR ...................................................... 54
2.8.2 Preventing Inappropriate Speculative Accesses ............................................................................. 54
2.8.2.1 Fetching Past an Interrupt-Causing or Interrupt-Returning Instruction .................................... 54
2.8.2.2 Fetching Past tw or twi Instructions ......................................................................................... 55
2.8.2.3 Fetching Past an Unconditional Branch ................................................................................... 55
2.8.2.4 Suggested Locations of Memory-Mapped Hardware ............................................................... 55
2.8.3 Summary ......................................................................................................................................... 56
2.9 User and Supervisor Modes .................................................................................................................... 56
2.9.1 MSR Bits and Exception Handling .................................................................................................. 56
2.9.2 Privileged Instructions ..................................................................................................................... 56
2.9.3 Privileged SPRs .............................................................................................................................. 57
2.9.4 Privileged DCRs .............................................................................................................................. 58
2.10 Synchronization ...................................................................................................................................... 58
2.10.1 Context Synchronization ............................................................................................................... 58
2.10.2 Execution Synchronization ............................................................................................................ 60
2.10.3 Storage Ordering and Synchronization ......................................................................................... 60
2.11 Implemented Instruction Set Summary ................................................................................................... 61
2.11.1 Instructions Specific to the PowerPC Embedded Environment ..................................................... 62
2.11.2 Storage Reference Instructions ..................................................................................................... 62
2.11.3 Arithmetic Instructions ................................................................................................................... 63
2.11.4 Logical Instructions ........................................................................................................................ 64
2.11.5 Compare Instructions .................................................................................................................... 64
2.11.6 Branch Instructions ........................................................................................................................ 64
2.11.6.1 CR Logical Instructions .......................................................................................................... 65
2.11.6.2 Rotate Instructions ................................................................................................................. 65
2.11.6.3 Shift Instructions .................................................................................................................... 65