AMCC PPC405 - Page 5

AMCC Proprietary 5
Revision 1.02 - September 10, 2007
PPC405 Processor
Preliminary User’s Manual
2.11.6.4 Cache Management Instructions ........................................................................................... 66
2.11.7 Interrupt Control Instructions ......................................................................................................... 66
2.11.8 TLB Management Instructions ...................................................................................................... 66
2.11.9 Processor Control Instructions ...................................................................................................... 67
2.11.10 Extended Mnemonics .................................................................................................................. 67
3. Cache Operations ........................................................................................................................... 69
3.1 ICU Features ............................................................................................................................................ 69
3.2 DCU Features ........................................................................................................................................... 69
3.3 ICU Organization ...................................................................................................................................... 69
3.3.1 ICU Operations ............................................................................................................................... 71
3.3.2 Instruction Cachability Control ........................................................................................................ 71
3.3.3 Instruction Cache Synonyms .......................................................................................................... 71
3.3.4 ICU Coherency ................................................................................................................................ 72
3.4 DCU Organization .................................................................................................................................... 72
3.4.1 DCU Operations .............................................................................................................................. 73
3.4.2 DCU Write Strategies ...................................................................................................................... 74
3.4.3 DCU Load and Store Strategies ...................................................................................................... 74
3.4.4 Data Cachability Control ................................................................................................................. 75
3.4.5 DCU Coherency .............................................................................................................................. 75
3.5 Cache Instructions .................................................................................................................................... 75
3.5.1 ICU Instructions ............................................................................................................................... 75
3.5.2 DCU Instructions ............................................................................................................................. 76
3.6 Cache Control and Debugging Features ................................................................................................ 77
3.6.1 CCR0 Programming Guidelines ...................................................................................................... 79
3.6.2 ICU Debugging ................................................................................................................................ 80
3.6.3 DCU Debugging .............................................................................................................................. 81
3.7 DCU Performance .................................................................................................................................... 81
3.7.1 Pipeline Stalls .................................................................................................................................. 81
3.7.2 Cache Operation Priorities .............................................................................................................. 82
3.7.3 Simultaneous Cache Operations .................................................................................................... 82
3.7.4 Sequential Cache Operations ......................................................................................................... 82
4. On-Chip Memory (OCM) ................................................................................................................. 85
4.1 OCM Addressing ...................................................................................................................................... 86
4.2 Store Data Bypass Behavior and Memory Coherency ............................................................................. 86
4.3 OCM Registers ......................................................................................................................................... 88
5. Memory Management ..................................................................................................................... 91
5.1 MMU Overview ......................................................................................................................................... 91
5.2 Address Translation .................................................................................................................................. 91
5.3 Translation Lookaside Buffer (TLB) .......................................................................................................... 92
5.3.1 Unified TLB ..................................................................................................................................... 92
5.3.2 TLB Fields ....................................................................................................................................... 93
5.3.2.1 Page Identification Fields ......................................................................................................... 93
5.3.2.2 Translation Field ...................................................................................................................... 94
5.3.2.3 Access Control Fields .............................................................................................................. 95
5.3.2.4 Storage Attribute Fields ........................................................................................................... 95
5.3.3 Shadow Instruction TLB .................................................................................................................. 96
5.3.3.1 ITLB Accesses ......................................................................................................................... 96
5.3.4 Shadow Data TLB ........................................................................................................................... 97
5.3.4.1 1 DTLB Accesses .................................................................................................................... 97
5.3.5 Shadow TLB Consistency ............................................................................................................... 97