AMCC PPC405 - Page 6

6 AMCC Proprietary
Revision 1.02 - September 10, 2007
PPC405 Processor
Preliminary User’s Manual
5.4 TLB-Related Interrupts ............................................................................................................................. 99
5.4.1 Data Storage Interrupt ..................................................................................................................... 99
5.4.2 Instruction Storage Interrupt ............................................................................................................ 99
5.4.3 Data TLB Miss Interrupt ................................................................................................................ 100
5.4.4 Instruction TLB Miss Interrupt ....................................................................................................... 100
5.5 TLB Management ................................................................................................................................... 100
5.5.1 TLB Search Instructions (tlbsx/tlbsx.) ............................................................................................ 100
5.5.2 TLB Read/Write Instructions (tlbre/tlbwe) ...................................................................................... 101
5.5.3 TLB Invalidate Instruction (tlbia) .................................................................................................... 101
5.5.4 TLB Sync Instruction (tlbsync) ....................................................................................................... 101
5.6 Recording Page References and Changes ............................................................................................ 101
5.7 Access Protection ................................................................................................................................... 102
5.7.1 Access Protection Mechanisms in the TLB ................................................................................... 102
5.7.1.1 General Access Protection ............................................................................................... 102
5.7.1.2 Execute Permissions ............................................................................................................. 102
5.7.1.3 Write Permissions .................................................................................................................. 102
5.7.1.4 Zone Protection ...................................................................................................................... 103
5.7.2 Access Protection for Cache Control Instructions ......................................................................... 104
5.7.3 Access Protection for String Instructions ....................................................................................... 105
5.8 Real-Mode Storage Attribute Control ...................................................................................................... 105
5.8.1 Storage Attribute Control Registers ............................................................................................... 106
5.8.1.1 Data Cache Write-through Register (DCWR) ........................................................................ 106
5.8.1.2 Data Cache Cachability Register (DCCR) ............................................................................. 106
5.8.1.3 Instruction Cache Cachability Register (ICCR) ...................................................................... 107
5.8.1.4 Storage Guarded Register (SGR) .......................................................................................... 107
5.8.1.5 Storage User-defined 0 Register (SU0R) .............................................................................. 107
5.8.1.6 Storage Little-Endian Register (SLER) .................................................................................. 107
6. Interrupt Handling ......................................................................................................................... 109
6.1 Architectural Definitions and Behavior .................................................................................................... 109
6.2 Behavior of the PPC405 Implementation ................................................................................................ 110
6.3 Interrupt Handling Priorities .................................................................................................................... 111
6.4 Critical and Noncritical Interrupts ........................................................................................................... 112
6.5 General Interrupt Handling Registers ..................................................................................................... 114
6.5.1 Machine State Register (MSR) ...................................................................................................... 114
6.5.2 Save/Restore Registers 0 and 1 (SRR0–SRR1) ........................................................................... 115
6.5.3 Save/Restore Registers 2 and 3 (SRR2–SRR3) ........................................................................... 115
6.5.4 Exception Vector Prefix Register (EVPR) ..................................................................................... 116
6.5.5 Exception Syndrome Register (ESR) ............................................................................................ 116
6.5.6 Data Exception Address Register (DEAR) .................................................................................... 118
6.6 Critical Input Interrupts ............................................................................................................................ 118
6.7 Machine Check Interrupts ....................................................................................................................... 118
6.7.1 Instruction Machine Check Handling ............................................................................................. 119
6.7.2 Data Machine Check Handling ...................................................................................................... 120
6.8 Data Storage Interrupt ............................................................................................................................ 120
6.9 Instruction Storage Interrupt ................................................................................................................... 121
6.10 External Interrupt .................................................................................................................................. 122
6.10.1 External Interrupt Handling .......................................................................................................... 122
6.11 Alignment Interrupt ............................................................................................................................... 123
6.12 Program Interrupt .................................................................................................................................. 123
6.13 System Call Interrupt ............................................................................................................................ 124