AMCC PPC405 - Page 7

AMCC Proprietary 7
Revision 1.02 - September 10, 2007
PPC405 Processor
Preliminary User’s Manual
6.14 Programmable Interval Timer (PIT) Interrupt ....................................................................................... 125
6.15 Fixed Interval Timer (FIT) Interrupt ....................................................................................................... 125
6.16 Watchdog Timer Interrupt ..................................................................................................................... 126
6.17 Data TLB Miss Interrupt ........................................................................................................................ 127
6.18 Instruction TLB Miss Interrupt ............................................................................................................... 127
6.19 Debug Interrupt ..................................................................................................................................... 128
7. Timer Facilities .............................................................................................................................. 129
7.1 Time Base .............................................................................................................................................. 130
7.1.1 Reading the Time Base ................................................................................................................. 131
7.1.2 Writing the Time Base ................................................................................................................... 131
7.2 Programmable Interval Timer (PIT) ...................................................................................................... 131
7.2.1 Fixed Interval Timer (FIT) .............................................................................................................. 132
7.3 Watchdog Timer ..................................................................................................................................... 133
7.4 Timer Status Register (TSR) .................................................................................................................. 135
7.5 Timer Control Register (TCR) ................................................................................................................. 135
8. Debugging ..................................................................................................................................... 137
8.1 Development Tool Support ..................................................................................................................... 137
8.2 Debug Interfaces .................................................................................................................................... 137
8.3 IEEE 1149.1 Test Access Port (JTAG Debug Port) ............................................................................... 137
8.3.1 JTAG Connector ........................................................................................................................... 138
8.3.2 JTAG Instructions .......................................................................................................................... 138
8.3.3 JTAG Boundary Scan ................................................................................................................... 138
8.3.4 JTAG Implementation ................................................................................................................... 139
8.3.5 JTAG ID Register .......................................................................................................................... 139
8.4 Trace Port .............................................................................................................................................. 139
8.5 Debug Modes ......................................................................................................................................... 139
8.5.1 Internal Debug Mode ..................................................................................................................... 140
8.5.2 External Debug Mode ................................................................................................................... 140
8.5.3 Debug Wait Mode ......................................................................................................................... 140
8.5.4 Real-time Trace Debug Mode ....................................................................................................... 141
8.6 Processor Control ................................................................................................................................... 142
8.7 Processor Status ................................................................................................................................... 142
8.8 Debug Registers ..................................................................................................................................... 142
8.8.1 Debug Control Registers ............................................................................................................... 143
8.8.1.1 Debug Control Register 0 (DBCR0) ....................................................................................... 143
8.8.1.2 Debug Control Register 1 (DBCR1) ....................................................................................... 144
8.8.2 Debug Status Register (DBSR) .................................................................................................... 145
8.8.3 Instruction Address Compare Registers (IAC1–IAC4) ................................................................. 147
8.8.4 Data Address Compare Registers (DAC1–DAC2) ..................................................................... 147
8.8.5 Data Value Compare Registers (DVC1–DVC2) ........................................................................ 147
8.8.6 Debug Events ................................................................................................................................ 147
8.8.7 Instruction Complete Debug Event ............................................................................................... 148
8.8.8 Branch Taken Debug Event .......................................................................................................... 148
8.8.9 Exception Taken Debug Event ...................................................................................................... 148
8.8.10 Trap Taken Debug Event ............................................................................................................ 149
8.8.11 Unconditional Debug Event ......................................................................................................... 149
8.8.12 IAC Debug Event ........................................................................................................................ 149
8.8.12.1 IAC Exact Address Compare ............................................................................................... 149
8.8.12.2 IAC Range Address Compare ............................................................................................. 149
8.8.13 DAC Debug Event ....................................................................................................................... 150