AMCC PPC405 - Page 20

20 AMCC Proprietary
Revision 1.02 - September 10, 2007
PPC405 Processor
Preliminary User’s Manual
GPR(r) General Purpose Register (GPR) r, where 0 ≤ r ≤ 31.
(GPR(r)) The contents of GPR r, where 0 ≤ r ≤ 31.
DCR(DCRN) A Device Control Register (DCR) specified by the DCRF field in an
mfdcr or mtdcr
instruction
SPR(SPRN) An SPR specified by the SPRF field in an
mfspr or mtspr instruction
TBR(TBRN) A Time Base Register (TBR) specified by the TBRF field in an
mftb instruction
GPRs RA, RB,
. . .
(Rx) The contents of a GPR, where x is A, B, S, or T
(RA|0) The contents of the register RA or 0, if the RA field is 0.
CR
FLD
The field in the condition register pointed to by a field of an instruction.
c
0:3
A 4-bit object used to store condition results in compare instructions.
n
b The bit or bit value b is replicated n times.
xx Bit positions which are don’t-cares.
CEIL(x) Least integer ≥ x.
EXTS(x) The result of extending
x on the left with sign bits.
PC Program counter.
RESERVE Reserve bit; indicates whether a process has reserved a block of storage.
CIA Current instruction address; the 32-bit address of the instruction being described by
a sequence of pseudocode. This address is used to set the next instruction address
(NIA). Does not correspond to any architected register.
NIA Next instruction address; the 32-bit address of the next instruction to be executed. In
pseudocode, a successful branch is indicated by assigning a value to NIA. For
instructions that do not branch, the NIA is CIA +4.
MS(addr, n) The number of bytes represented by
n at the location in main storage represented by
addr.
EA Effective address; the 32-bit address, derived by applying indexing or indirect
addressing rules to the specified operand, that specifies a location in main storage.
EA
b
A bit in an effective address.
EA
b:b
A range of bits in an effective address.
ROTL((RS),n) Rotate left; the contents of RS are shifted left the number of bits specified by
n.
MASK(MB,ME) Mask having 1s in positions MB through ME (wrapping if MB > ME) and 0s
elsewhere.
instruction(EA) An instruction operating on a data or instruction cache block associated with an EA.