AMCC PPC405 - Page 78

78 AMCC Proprietary
Revision 1.02 - September 10, 2007
PPC405 Processor
Preliminary User’s Manual
10:11 IPP ICU PLB Priority Bits 0:1
00 Lowest ICU PLB priority
01 Next to lowest ICU PLB priority
10 Next to highest ICU PLB priority
11 Highest ICU PLB priority
12 DPE Data Cache Parity Enable
0 Disable
1 Enable
13 DPP Data Cache Parity Precision
0 Imprecise
1 Precise
14 U0XE Enable U0 Exception
0 Disables the U0 exception
1 Enables the U0 exception
15 LDBE Load Debug Enable
0 Disable
1 Enable
When enabled, load data is visible on data-side
OCM.
16:17
Reserved
18 IPE Instruction Cache Parity Enable
0 Disable
1 Enable
19 TPE Translation Lookaside Buffer (TLB) Parity Enable
0 Disable
1 Enable
20 PFC ICU Prefetching for Cacheable Regions
0 Disables prefetching for cacheable regions
1 Enables prefetching for cacheable regions
21 PFNC ICU Prefetching for Non Cacheable Regions
0 Disables prefetching for non cacheable regions
1 Enables prefetching for non cacheable regions
22 NCRS Non cacheable ICU request size
0 Requests are for four-word lines
1 Requests are for eight-word lines
23 FWOA Fetch Without Allocate
0 An ICU miss results in a line fill.
1 An ICU miss does not cause a line fill, but results
in a non cacheable fetch.
24:26
Reserved
27 CIS Cache Information Select
0 Information is cache data.
1 Information is cache tag.
28 PRS Parity Read Select
Information passed is selected by CCR0[CIS] and
CCR0[CWS].
0 Pass data or tag
1 Pass parity information
29:30
Reserved
31 CWS Cache Way Select
0 Cache way is A.
1 Cache way is B.