Intel 6 SERIES CHIPSET - DATASHEET 01-2011

PCH Pin States
104 Datasheet
UnMultiplexed GPIO Signals
GPIO8
7
Suspend High High Defined Defined Defined Defined
GPIO15
7
Suspend Low Low Defined Defined Defined Defined
GPIO24 Suspend Low Low Defined Defined Defined Defined
GPIO27
7
(Non-Deep
S4/S5 mode)
DSW High-Z High-Z High-Z High-Z High-Z High-Z
GPIO27
7
(Deep S4/S5
mode)
DSW High-Z High-Z High-Z High-Z High-Z High-Z
GPIO28 Suspend High Low Low Low Low Low
GPIO57 Suspend Low High-Z (Input) Defined Defined Defined Defined
Multiplexed GPIO Signals used as GPIO only
GPIO0 Core
High-Z
(Input)
High-Z (Input) Defined Defined Off Off
GPIO[17,7,6,1]
8
Core High-Z High-Z High-Z High-Z Off Off
GPIO35 Core Low Low Defined Defined Off Off
GPIO50 Core High-Z High-Z High-Z High-Z Off Off
GPIO[55,53,51] Core High High High High Off Off
GPIO52 Core High-Z High-Z High-Z High-Z Off Off
GPIO54 Core High-Z High-Z High-Z High-Z Off Off
GPIO[71:68] Core High-Z High-Z High-Z High-Z Off Off
SPI Interface
SPI_CS0# ASW High
18
High Defined Defined Defined Defined
SPI_CS1#
7
ASW High
18
High Defined Defined Defined Defined
SPI_MOSI
7
ASW Low
18
Low Defined Defined Defined Defined
SPI_CLK ASW Low
18
Low Running Running Defined Defined
Controller Link
CL_CLK1
6
Suspend High/Low
13
High/Low
13
Defined Defined Defined Defined
CL_DATA1
6
Suspend High/Low
13
High/Low
13
Defined Defined Defined Defined
CL_RST1#
6
Suspend Low High Defined High High High
Table 3-3. Power Plane and States for Output and I/O Signals for Mobile Configurations
(Sheet 4 of 6)
Signal Name
Power
Plane
During
Reset
1
Immediately
after Reset
1
C-x
states
S0/S1 S3 S4/S5