Intel 6 SERIES CHIPSET - DATASHEET 01-2011

Datasheet 105
PCH Pin States
LVDS Signals
LVDSA_DATA[3:0],
LVDSA_DATA#[3:0]
Core High-Z High-Z
Defined/
High-Z
12
Defined/
High-Z
12
Off Off
LVDSA_CLK,
LVDSA_CLK#
Core High-Z High-Z
Defined/
High-Z
12
Defined/
High-Z
12
Off Off
LVDSB_DATA[3:0],
LVDSB_DATA#[3:0]
Core High-Z High-Z
Defined/
High-Z
12
Defined/
High-Z
12
Off Off
LVDSB_CLK,
LVDSB_CLK#
Core High-Z High-Z
Defined/
High-Z
12
Defined/
High-Z
12
Off Off
L_DDC_CLK Core High-Z High-Z High-Z High-Z Off Off
L_DDC_DATA Core Low High-Z High-Z High-Z Off Off
L_VDD_EN Core Low Low
Low/
High-Z
12
Low/
High-Z
12
Off Off
L_BKLTEN Core Low Low
Low/
High-Z
12
Low/
High-Z
12
Off Off
L_BKLTCTL Core Low Low
Low/
High-Z
12
Low/
High-Z
12
Off Off
L_CTRL_CLK Core High-Z High-Z High-Z High-Z Off Off
L_CTRL_DATA Core High-Z High-Z High-Z High-Z Off Off
LVD_VBG,
LVD_VREFH,
LVD_VREFL
Core High-Z High-Z High-Z High-Z Off Off
Analog Display / CRT DAC Signals
CRT_RED,
CRT_GREEN,
CRT_BLUE
Core High-Z High-Z Defined Defined Off Off
DAC_IREF Core High-Z Low Low Low Off Off
CRT_HSYNC Core Low Low Low Low Off Off
CRT_VSYNC Core Low Low Low Low Off Off
CRT_DDC_CLK Core High-Z High-Z High-Z High-Z Off Off
CRT_DDC_DATA Core High-Z High-Z High-Z High-Z Off Off
CRT_IRTN Core High-Z High-Z High-Z High-Z Off Off
Intel
®
Flexible Display Interface
FDI_FSYNC[1:0] Core High-Z High-Z Defined Defined Off Off
FDI_LSYNC[1:0] Core High-Z High-Z Defined Defined Off Off
FDI_INT Core High-Z High-Z Defined Defined Off Off
Table 3-3. Power Plane and States for Output and I/O Signals for Mobile Configurations
(Sheet 5 of 6)
Signal Name
Power
Plane
During
Reset
1
Immediately
after Reset
1
C-x
states
S0/S1 S3 S4/S5