Intel 6 SERIES CHIPSET - DATASHEET 01-2011

Datasheet 691
Integrated Intel
®
High Definition Audio Controller Registers
17.1.1.17 INTLN—Interrupt Line Register
(Intel
®
High Definition Audio Controller—D27:F0)
Address Offset: 3Ch Attribute: R/W
Default Value: 00h Size: 8 bits
17.1.1.18 INTPN—Interrupt Pin Register
(Intel
®
High Definition Audio Controller—D27:F0)
Address Offset: 3Dh Attribute: RO
Default Value: See Description Size: 8 bits
17.1.1.19 HDCTL—Intel
®
High Definition Audio Control Register
(Intel
®
High Definition Audio Controller—D27:F0)
Address Offset: 40h Attribute: RO
Default Value: 01h Size: 8 bits
Bit Description
7:0
Interrupt Line (INT_LN) — R/W. This data is not used by the PCH. It is used to
communicate to software the interrupt line that the interrupt pin is connected to.
Bit Description
7:4 Reserved.
3:0
Interrupt Pin — RO. This reflects the value of D27IP.ZIP (Chipset Config
Registers:Offset 3110h:bits 3:0).
Bit Description
7:1 Reserved.
0
Intel
®
High Definition Signal Mode — RO.
This bit is hardwired to 1 (High Definition Audio mode).