Integrated Intel
®
High Definition Audio Controller Registers
692 Datasheet
17.1.1.20 TCSEL—Traffic Class Select Register
(Intel
®
High Definition Audio Controller—D27:F0)
Address Offset: 44h Attribute: R/W
Default Value: 00h Size: 8 bits
Function Level Reset: No
This register assigned the value to be placed in the TC field. CORB and RIRB data will
always be assigned TC0.
17.1.1.21 DCKCTL—Docking Control Register (Mobile Only)
(Intel
®
High Definition Audio Controller—D27:F0)
Address Offset: 4Ch Attribute: R/W, RO
Default Value: 00h Size: 8 bits
Function Level Reset: No
Bit Description
7:3 Reserved.
2:0
Intel
®
HIgh Definition Audio Traffic Class Assignment (TCSEL)— R/W.
This register assigns the value to be placed in the Traffic Class field for input data,
output data, and buffer descriptor transactions.
000 = TC0
001 = TC1
010 = TC2
011 = TC3
100 = TC4
101 = TC5
110 = TC6
111 = TC7
NOTE: These bits are not reset on D3
HOT
to D0 transition; however, they are reset by
PLTRST#.
Bit Description
7:1 Reserved.
0
Dock Attach (DA) — R/W / RO. Software writes a 1 to this bit to initiate the docking
sequence on the HDA_DOCK_EN# and HDA_DOCK_RST# signals. When the docking
sequence is complete, hardware will set the Dock Mated (GSTS.DM) status bit to 1.
Software writes a 0 to this bit to initiate the undocking sequence on the
HDA_DOCK_EN# and HDA_DOCK_RST# signals. When the undocking sequence is
complete, hardware will set the Dock Mated (GSTS.DM) status bit to 0.
Note that software must check the state of the Dock Mated (GSTS.DM) bit prior to
writing to the Dock Attach bit. Software shall only change the DA bit from 0 to 1 when
DM=0. Likewise, software shall only change the DA bit from 1 to 0 when DM=1. If
these rules are violated, the results are undefined.
Note that this bit is Read Only when the DCKSTS.DS bit = 0.
To Next Page
Loading...
Need help?
General
