Datasheet 899
Intel® Management Engine Interface (MEI) Subsystem Registers (D22:F0)
23.5.15 CAPP—Capabilities List Pointer Register
(IDER—D22:F2)
Address Offset: 34h Attribute: RO
Default Value: C8h Size: 8 bits
23.5.16 INTR—Interrupt Information Register
(IDER—D22:F2)
Address Offset: 3C–3Dh Attribute: R/W, RO
Default Value: 0300h Size: 16 bits
23.5.17 PID—PCI Power Management Capability ID Register
(IDER—D22:F2)
Address Offset: C8–C9h Attribute: RO
Default Value: D001h Size: 16 bits
Bit Description
7:0
Capability Pointer (CP)— R/WO. This field indicates that the first capability pointer
is offset C8h (the power management capability).
Bit Description
15:8
Interrupt Pin (IPIN) — RO. A value of 1h/2h/3h/4h indicates that this function
implements legacy interrupt on INTA/INTB/INTC/INTD, respectively
FunctionValueINTx
(2 IDE)03hINTC
7:0
Interrupt Line (ILINE)— R/W. The value written in this register indicates which
input of the system interrupt controller, the device's interrupt pin is connected to.
This value is used by the OS and the device driver, and has no affect on the
hardware.
Bit Description
15:8 Next Capability (NEXT) — RO. Its value of D0h points to the MSI capability.
7:0 Cap ID (CID)— RO. This field indicates that this pointer is a PCI power management.
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